Inventor profile of:

HeeJo Chi

City:

Kyoungki-do

Country:

South Korea

Published Applications:

38

Last publication date:

2018-04-19

Top Assignees for applications by HeeJo Chi

The entities that hold a legal rights for patent applications filed by inventor Chi HeeJo:

Recent patent applications by Chi HeeJo

HeeJo Chi from Kyoungki-do, KR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2018-04-19
US20180108542A1
Electricity

Semiconductor device and method of forming interposer with opening to contain semiconductor die

#2 | 2017-10-26
US20170309572A1
Electricity

Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP

#3 | 2017-08-31
US20170250154A1
Electricity

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

#4 | 2016-11-10
US20160329310A1
Electricity

Methods of forming conductive and insulating layers

#5 | 2016-08-11
US20160233168A1
Electricity

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

#6 | 2016-06-09
US20160163675A1
Electricity

Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form

#7 | 2015-10-01
US20150279778A1
Electricity

Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring

#8 | 2015-09-24
US20150270237A1
Electricity

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

#9 | 2015-05-07
US20150123273A1
Electricity

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

#10 | 2015-04-02
US20150091157A9
Electricity

Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer

#11 | 2015-01-01
US20150004756A1
Electricity

Methods of forming conductive and insulating layers

#12 | 2015-01-01
US20150004750A1
Electricity

Methods of Forming Conductive Materials on Contact Pads

#13 | 2015-01-01
US20150004748A1
Electricity

Methods of forming conductive jumper traces

#14 | 2014-12-18
US20140367848A1
Electricity

Semiconductor Device and Method of Making an Embedded Wafer Level Ball Grid Array (EWLB) Package on Package (POP) Device With a Slotted Metal Carrier Interposer

#15 | 2014-12-11
US20140361423A1
Electricity

Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die

#16 | 2014-10-02
US20140295618A1
Electricity

Methods of manufacturing flip chip semiconductor packages using double-sided thermal compression bonding

#17 | 2014-06-26
US20140175661A1
Electricity

Semiconductor device and method of making bumpless flipchip interconnect structures

#18 | 2014-06-26
US20140175640A1
Electricity

Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form

#19 | 2014-06-26
US20140175639A1
Electricity

Semiconductor device and method of simultaneous molding and thermalcompression bonding

#20 | 2013-11-14
US20130299982A1
Electricity

Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die

#21 | 2013-11-14
US20130299974A1
Electricity

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

#22 | 2013-09-26
US20130249104A1
Electricity

Semiconductor device and method of forming conductive layer over metal substrate for electrical interconnect of semiconductor die

#23 | 2013-05-02
US20130105970A1
Electricity

Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe

#24 | 2013-04-25
US20130099378A1
Electricity

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

#25 | 2013-04-11
US20130087898A1
Electricity

Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

#26 | 2013-01-03
US20130001762A1
Electricity

Semiconductor Device and Method of Using Leadframe Bodies to Form Openings Through Encapsulant for Vertical Interconnect of Semiconductor Die

#27 | 2012-11-22
US20120292745A1
Electricity

Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer

#28 | 2012-10-16
US13153286
-

Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die

#29 | 2012-07-05
US20120168916A1
Electricity

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

#30 | 2012-06-21
US20120153505A1
Electricity

Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint

#31 | 2012-06-21
US20120153467A1
Electricity

Semiconductor device with thin profile WLCSP with vertical interconnect over package footprint

#32 | 2012-05-17
US20120119388A1
Electricity

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

#33 | 2011-12-01
US20110291249A1
Electricity

Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe

#34 | 2011-11-17
US20110278707A1
Electricity

Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

#35 | 2011-08-04
US20110186977A1
Electricity

Method of forming thin profile WLCSP with vertical interconnect over package footprint

#36 | 2011-03-24
US20110068459A1
Electricity

Semiconductor device and method of forming interposer with opening to contain semiconductor die

#37 | 2011-03-24
US20110068444A1
Electricity

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

#38 | 2011-03-03
US20110049695A1
Electricity

Semiconductor device and method of forming pre-molded semiconductor die having bumps embedded in encapsulant

InventorID:

4286 ⎘