Kyoung-gi-Do
South Korea
17
2014-10-30
The entities that hold a legal rights for patent applications filed by inventor Cho SungWon:
SungWon Cho from Kyoung-gi-Do, KR has applied for patents for these inventions. The list has both pending applications and granted patents:
Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer
#2 | 2014-06-26Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
#3 | 2014-01-09Semiconductor Device and Method of Forming Electrical Interconnection Between Semiconductor Die and Substrate with Continuous Body of Solder Tape
#4 | 2013-09-12Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
#5 | 2013-06-20Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
#6 | 2013-06-13Semiconductor device and method of making single layer substrate with asymmetrical fibers and reduced warpage
#7 | 2013-02-07Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
#8 | 2013-01-03Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump
#9 | 2012-12-06Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
#10 | 2012-12-06Semiconductor device and method of forming WLCSP structure using protruded MLP
#11 | 2012-08-30Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer
#12 | 2012-08-30Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump
#13 | 2012-08-23Semiconductor device and method of forming WLCSP structure using protruded MLP
#14 | 2012-07-26Semiconductor device and method of forming column interconnect structure to reduce wafer stress
#15 | 2012-02-23Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
#16 | 2011-10-20Semiconductor device and method of forming electrical interconnection between semiconductor die and substrate with continuous body of solder tape
#17 | 2011-05-05Semiconductor device and method of forming column interconnect structure to reduce wafer stress
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