Livermore, California
United States
26
2019-09-05
The entities that hold a legal rights for patent applications filed by inventor Sinha Jaydeep:
Jaydeep Sinha from Livermore, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool
#2 | 2019-07-16Systems and methods for wafer structure uniformity monitoring using interferometry wafer geometry tool
#3 | 2018-12-20Prediction based chucking and lithography control optimization
#4 | 2018-01-09Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool
#5 | 2017-07-11Systems and methods for wafer surface feature detection and quantification
#6 | 2017-05-09Detection of selected defects in relatively noisy inspection data
#7 | 2016-12-22Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements
#8 | 2016-11-03Hybrid phase unwrapping systems and methods for patterned wafer measurement
#9 | 2016-09-29System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
#10 | 2016-08-18Prediction based chucking and lithography control optimization
#11 | 2016-06-09Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry
#12 | 2016-05-31Detection of selected defects in relatively noisy inspection data
#13 | 2016-03-10Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance
#14 | 2015-10-22Predictive wafer modeling based focus error prediction using correlations of wafers
#15 | 2015-10-22Patterned wafer geometry measurements for semiconductor process controls
#16 | 2015-07-30Using wafer geometry to improve scanner correction effectiveness for overlay control
#17 | 2015-07-21Statistical overlay error prediction for feed forward and feedback correction of overlay errors, root cause analysis and process control
#18 | 2015-04-30Process-induced distortion prediction and feedforward and feedback correction of overlay errors
#19 | 2014-12-04Using wafer geometry to improve scanner correction effectiveness for overlay control
#20 | 2014-09-18Bright-field differential interference contrast system with scanning beams of round and elliptical cross-sections
#21 | 2014-04-24Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool
#22 | 2014-04-17System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
#23 | 2013-09-12Systems and methods of advanced site-based nanotopography for wafer surface metrology
#24 | 2012-07-12Methods and systems for improved localized feature quantification in surface metrology tools
#25 | 2011-09-08Systems and methods for wafer edge feature detection and quantification
#26 | 2011-07-14Site based quantification of substrate topography and its relation to lithography defocus and overlay
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