San Jose, California
United States
35
2014-08-21
The entities that hold a legal rights for patent applications filed by inventor Randolph Mark:
Mark Randolph from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
APPARATUS AND METHOD TO REDUCE BIT LINE DISTURBS
#2 | 2013-09-12Method and apparatus for protection against process-induced charging
#3 | 2010-12-16System and method for reducing process-induced charging
#4 | 2010-09-23Strapping contact for charge protection
#5 | 2010-02-04Flash memory programming and verification with reduced leakage current
#6 | 2009-07-30ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM
#7 | 2009-06-25ELECTRONIC DEVICE INCLUDING A SILICON NITRIDE LAYER AND A PROCESS OF FORMING THE SAME
#8 | 2009-06-18High K stack for non-volatile memory
#9 | 2008-11-13Multi-phase wordline erasing for flash memory
#10 | 2008-06-26Method and apparatus for protection against process-induced charging
#11 | 2008-06-26Variable salicide block for resistance equalization in an array
#12 | 2008-06-19Strapping contact for charge protection
#13 | 2008-06-12P-channel NAND in isolated N-well
#14 | 2008-06-03Oxygen elimination for device processing
#15 | 2008-05-29Select transistor using buried bit line from core
#16 | 2008-04-29Memory cell having enhanced high-K dielectric
#17 | 2008-03-04Method for determining wordline critical dimension in a memory array and related structure
#18 | 2007-11-22System and method for reducing process-induced charging
#19 | 2007-10-11Flash memory programming and verification with reduced leakage current
#20 | 2007-09-20Memory cell system using silicon-rich nitride
#21 | 2007-08-28System and method for reducing process-induced charging
#22 | 2007-05-24Methods and systems for high write performance in multi-bit flash memory devices
#23 | 2007-04-17Methods and systems for high write performance in multi-bit flash memory devices
#24 | 2007-02-13LDC implant for mirrorbit to improve Vt roll-off and form sharper junction
#25 | 2007-01-30Methods and systems for reducing the threshold voltage distribution following a memory cell erase
#26 | 2007-01-23System and method for erasing a memory cell
#27 | 2006-12-28Flash memory cell and methods for programming and erasing
#28 | 2006-11-30Read-only memory array with dielectric breakdown programmability
#29 | 2006-10-26Self-aligned STI SONOS
#30 | 2006-10-10Flash memory cell and methods for programming and erasing
#31 | 2006-09-28High K stack for non-volatile memory
#32 | 2006-07-04One stack with steam oxide for charge retention
#33 | 2006-05-04System and method for protecting semiconductor devices
#34 | 2005-08-23Ramp source hot-hole programming for trap based non-volatile memory devices
#35 | 2005-05-31ESD implant following spacer deposition
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