San Jose, California
United States
39
2019-12-19
The entities that hold a legal rights for patent applications filed by inventor HADDAD Sameer:
Sameer HADDAD from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Memory first process flow and device
#2 | 2018-12-20Memory first process flow and device
#3 | 2017-05-18Memory first process flow and device
#4 | 2016-10-06Memory first process flow and device
#5 | 2016-04-21Charge trapping split gate embedded flash memory and associated methods
#6 | 2014-12-04Metal-insualtor-metal (MIM) device and method of formation thereof
#7 | 2014-10-09Modified local segmented self-boosting of memory cell channels
#8 | 2014-09-30Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof
#9 | 2014-06-19Charge trapping split gate device and method of fabricating same
#10 | 2014-06-19Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
#11 | 2014-06-19Memory first process flow and device
#12 | 2014-06-19Process charging protection for split gate charge trapping flash
#13 | 2013-09-12Metal-insulator-metal (MIM) device and method of formation thereof
#14 | 2012-11-01Damascene metal-insulator-metal (MIM) device with improved scaleability
#15 | 2012-04-05Method of programming, erasing and repairing a memory device
#16 | 2011-10-20Resistive memory array using P-I-N diode select device and methods of fabrication thereof
#17 | 2011-02-03Memory device with improved data retention
#18 | 2010-08-19Pin diode device and architecture
#19 | 2009-04-30Erase, programming and leakage characteristics of a resistive memory device
#20 | 2009-04-30Metal-insulator-metal (MIM) device and method of formation thereof
#21 | 2009-03-19Test structures for development of metal-insulator-metal (MIM) devices
#22 | 2008-06-19Resistive memory array using P-I-N diode select device and methods of fabrication thereof
#23 | 2008-06-05Method of programming, erasing and repairing a memory device
#24 | 2008-06-05Damascene metal-insulator-metal (MIM) device
#25 | 2008-06-05Method of erasing a resistive memory device
#26 | 2008-06-05Test structures for development of metal-insulator-metal (MIM) devices
#27 | 2008-06-05Method of fabricating metal-insulator-metal (MIM) device with stable data retention
#28 | 2008-05-29Damascene metal-insulator-metal (MIM) device with improved scaleability
#29 | 2008-05-15Method of selecting operating characteristics of a resistive memory device
#30 | 2007-10-30Method of programming a resistive memory device
#31 | 2007-10-23Resistive memory device with improved data retention
#32 | 2007-02-13LDC implant for mirrorbit to improve Vt roll-off and form sharper junction
#33 | 2006-11-16Resistive memory device with improved data retention and reduced power
#34 | 2006-09-28Memory device with improved data retention
#35 | 2006-01-24Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices
#36 | 2005-11-17Bitline implant utilizing dual poly
#37 | 2005-10-11Reduced silicon gouging and common source line resistance in semiconductor devices
#38 | 2005-08-23Ramp source hot-hole programming for trap based non-volatile memory devices
#39 | 2005-07-14Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell
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