Nepean
Canada
36
2026-07-02
The entities that hold a legal rights for patent applications filed by inventor Amer Maher:
Maher Amer from Nepean, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY MODULE AND METHOD FOR WRITING DATA THERETO
#2 | 2026-07-02MEMORY MODULE INCLUDING A NON-VOLATILE WRITE CACHE AND METHOD FOR OPERATING THE MEMORY MODULE
#3 | 2026-07-02MEMORY SYSTEM AND METHOD FOR GENERATING A CHECKPOINT OF A MEMORY DEVICE
#4 | 2022-12-22System and method of interfacing co-processors and input/output devices via a main memory system
#5 | 2021-12-30System and method for providing a configurable timing control for a memory system
#6 | 2021-10-14System and method of interfacing co-processors and input/output devices via a main memory system
#7 | 2021-01-14System and method of interfacing co-processors and input/output devices via a main memory system
#8 | 2021-01-07System and method for implementing a multi-threaded device driver in a computer system
#9 | 2020-08-20System and method for providing a configurable timing control for a memory system
#10 | 2019-10-03HARDWARE BASED VIRTUAL MEMORY MANAGEMENT
#11 | 2019-07-11System and method of interfacing co-processors and input/output devices via a main memory system
#12 | 2019-02-28System and method for implementing a multi-threaded device driver in a computer system
#13 | 2019-02-07System and method for providing a configurable timing control for a memory system
#14 | 2016-12-29System and method of interfacing co-processors and input/output devices via a main memory system
#15 | 2016-12-22SYSTEM AND METHOD FOR OFFSETTING THE DATA BUFFER LATENCY OF A DEVICE IMPLEMENTING A JEDEC STANDARD DDR-4 LRDIMM CHIPSET
#16 | 2015-12-03SYSTEM AND METHOD FOR BOOTING FROM A NON-VOLATILE MEMORY
#17 | 2015-11-12SYSTEM AND METHOD OF ACCESSING AND CONTROLLING A CO-PROCESSOR AND/OR INPUT/OUTPUT DEVICE VIA REMOTE DIRECT MEMORY ACCESS
#18 | 2015-11-12SYSTEM AND METHOD OF IMPLEMENTING AN OBJECT STORAGE DEVICE ON A COMPUTER MAIN MEMORY SYSTEM
#19 | 2015-10-29SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM
#20 | 2015-10-29System and method of interfacing co-processors and input/output devices via a main memory system
#21 | 2015-10-15System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset
#22 | 2015-08-13Load reduction dual in-line memory module (LRDIMM) and method for programming the same
#23 | 2014-08-28Load reduction dual in-line memory module (LRDIMM) and method for programming the same
#24 | 2014-08-21System and method for providing a command buffer in a memory system
#25 | 2014-08-21System and method for unlocking additional functions of a module
#26 | 2014-08-21System and method for providing an address cache for memory map learning
#27 | 2014-08-07System and method of interfacing co-processors and input/output devices via a main memory system
#28 | 2013-09-12Load reduction dual in-line memory module (LRDIMM) and method for programming the same
#29 | 2012-08-09System and method of interfacing co-processors and input/output devices via a main memory system
#30 | 2010-03-18Load reduction dual in-line memory module (LRDIMM) and method for programming the same
#31 | 2008-08-19Parallel scrambler/descrambler
#32 | 2008-07-17Optimized FFT/IFFT module
#33 | 2008-04-17Parallel convolutional encoder
#34 | 2008-01-08Parallel convolutional encoder
#35 | 2007-08-02Memory system and method for use in trellis-based decoding
#36 | 2005-03-17Optimized FFT/IFFT module
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