Inventor profile of:

Cyrus E. Tabery

City:

Santa Clara, California

Country:

United States

Published Applications:

18

Last publication date:

2011-03-29

Top Assignees for applications by Cyrus E. Tabery

The entities that hold a legal rights for patent applications filed by inventor Tabery Cyrus E.:

Recent patent applications by Tabery Cyrus E.

Cyrus E. Tabery from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-03-29
US11625190
-

Methods for forming small contacts

#2 | 2010-12-21
US10838704
-

Wafer assembly having a contrast enhancing top anti-reflecting coating and method of lithographic processing

#3 | 2010-06-22
US10790457
-

Method for removal of immersion lithography medium in immersion lithography processes

#4 | 2009-06-02
US10790590
-

System and method for designing an integrated circuit device

#5 | 2008-10-07
US10863392
-

Formation of semiconductor devices to achieve <100> channel orientation

#6 | 2007-12-25
US10790381
-

Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin

#7 | 2007-10-02
US10791259
-

Lithography mask utilizing asymmetric light source

#8 | 2007-09-06
US20070209030A1
Physics

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

#9 | 2007-03-20
US10817132
-

System and method for design rule creation and selection

#10 | 2007-02-27
US10728909
-

Methods for forming small contacts

#11 | 2006-10-17
US10790567
-

Patterning with rigid organic under-layer

#12 | 2006-08-15
US10933424
-

End-of-range defect minimization in semiconductor device

#13 | 2006-05-30
US11003574
-

Method for forming wordlines having irregular spacing in a memory array

#14 | 2005-10-13
US20050229125A1
Physics

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

#15 | 2005-10-06
US20050221233A1
Physics

System and method for fabricating contact holes

#16 | 2005-05-19
US20050104091A1
Electricity

Self aligned damascene gate

#17 | 2005-03-03
US20050048223A1
Physics

Method and apparatus for elimination of bubbles in immersion medium in immersion lithography systems

#18 | 2005-02-15
US10459589
-

FinFET gate formation using reverse trim and oxide polish

InventorID:

4484013 ⎘