Inventor profile of:

Ashish Jain

City:

Austin, Texas

Country:

United States

Published Applications:

36

Last publication date:

2025-12-18

Top Assignees for applications by Ashish Jain

The entities that hold a legal rights for patent applications filed by inventor Jain Ashish:

Recent patent applications by Jain Ashish

Ashish Jain from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-12-18
US20250383923A1
Physics

WORKLOAD SCHEDULING BASED ON VOLTAGE DROOP CHARACTERISTICS

#2 | 2025-06-26
US20250208676A1
Physics

VOLTAGE MARGIN OPTIMIZATION BASED ON WORKLOAD SENSITIVITY

#3 | 2025-04-03
US20250111121A1
Physics

RUNTIME OPTIMIZATION OF ACTIVE INTERPOSER DIES FROM DIFFERENCE PROCESS BINS

#4 | 2025-04-03
US20250110525A1
Physics

SYSTEMS AND METHODS FOR ENABLING A FEATURE OF A SEMICONDUCTOR DEVICE

#5 | 2024-12-19
US20240419481A1
Physics

METHOD AND APPARATUS TO MIGRATE MORE SENSITIVE WORKLOADS TO FASTER CHIPLETS

#6 | 2024-12-05
US20240403242A1
Physics

DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE

#7 | 2024-10-03
US20240334340A1
Electricity

DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI

#8 | 2024-10-03
US20240331659A1
Physics

POWER MANAGEMENT OF DISPLAY DATA DURING AN IDLE SCREEN

#9 | 2024-10-03
US20240329720A1
Physics

STORING CONTIGUOUS DISPLAY CONTENT IN EACH DRAM FOR IDLE STATIC SCREEN POWER SAVING

#10 | 2024-09-26
US20240319781A1
Physics

LATENCY REDUCTION FOR TRANSITIONS BETWEEN ACTIVE STATE AND SLEEP STATE OF AN INTEGRATED CIRCUIT

#11 | 2024-06-27
US20240211023A1
Physics

Buffer display data in a chiplet architecture

#12 | 2024-06-27
US20240211014A1
Physics

POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION

#13 | 2024-04-04
US20240111442A1
Physics

On-Demand Regulation of Memory Bandwidth Utilization to Service Requirements of Display

#14 | 2024-04-04
US20240111351A1
Physics

Frequency/state based power management thresholds

#15 | 2024-03-28
US20240106438A1
Electricity

Droop detection and control of digital frequency-locked loop

#16 | 2024-03-28
US20240106423A1
Electricity

Leveraging an Adaptive Oscillator for Fast Frequency Changes

#17 | 2024-03-28
US20240103754A1
Physics

Memory Power Performance State Optimization During Image Display

#18 | 2024-01-25
US20240029488A1
Physics

POWER MANAGEMENT BASED ON FRAME SLICING

#19 | 2024-01-04
US20240004725A1
Physics

ADAPTIVE POWER THROTTLING SYSTEM

#20 | 2024-01-04
US20240004448A1
Physics

PLATFORM EFFICIENCY TRACKER

#21 | 2023-12-21
US20230409392A1
Physics

BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS

#22 | 2023-10-26
US20230341922A1
Physics

Dynamic cache bypass for power savings

#23 | 2022-06-16
US20220189576A1
Physics

Mission mode Vmin prediction and calibration

#24 | 2022-04-28
US20220130342A1
Physics

Refreshing displays using on-die cache

#25 | 2017-10-19
US20170300101A1
Physics

REDIRECTING MESSAGES FROM IDLE COMPUTE UNITS OF A PROCESSOR

#26 | 2016-12-29
US20160378168A1
Physics

DYNAMIC POWER MANAGEMENT OPTIMIZATION

#27 | 2016-10-20
US20160306406A1
Physics

Performance state selection for low activity scenarios

#28 | 2016-09-15
US20160266629A1
Physics

CHANGING POWER LIMITS BASED ON DEVICE STATE

#29 | 2016-09-15
US20160266628A1
Physics

Power management to change power limits based on device skin temperature

#30 | 2015-10-01
US20150277521A1
Physics

Dynamic power allocation based on PHY power estimation

#31 | 2015-09-24
US20150268713A1
Physics

ENERGY-AWARE BOOSTING OF PROCESSOR OPERATING POINTS FOR LIMITED DURATION WORKLOADS

#32 | 2015-07-09
US20150193259A1
Physics

BOOSTING THE OPERATING POINT OF A PROCESSING DEVICE FOR NEW USER ACTIVITIES

#33 | 2015-03-12
US20150073611A1
Physics

Estimating leakage currents based on rates of temperature overages or power overages

#34 | 2015-01-01
US20150006925A1
Physics

Allocating power to compute units based on energy efficiency

#35 | 2015-01-01
US20150006924A1
Physics

Selection of an operating point of a memory physical layer interface and a memory controller based on memory bandwidth utilization

#36 | 2013-09-19
US20130246820A1
Physics

Method for adaptive performance optimization of the soc

InventorID:

448574 ⎘