Moscow
Russian Federation
36
2015-08-13
The entities that hold a legal rights for patent applications filed by inventor Gasanov Elyar E.:
Elyar E. Gasanov from Moscow, RU has applied for patents for these inventions. The list has both pending applications and granted patents:
Systems and Methods for Rank Deficient Encoding
#2 | 2015-08-13Systems and methods for area efficient data encoding
#3 | 2014-08-07RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING
#4 | 2014-02-06HIGH SPEED ADD-COMPARE-SELECT CIRCUIT
#5 | 2013-09-12Optimization of data processors with irregular patterns
#6 | 2013-01-17Variable parity encoder
#7 | 2012-11-08Two-pass linear complexity task scheduler
#8 | 2012-11-08Parallel decoder for multiple wireless standards
#9 | 2012-11-01Timer manager architecture based on binary heap
#10 | 2012-06-28COMPUTATION OF JACOBIAN LOGARITHM OPERATION
#11 | 2012-06-07Radix-4 viterbi forward error correction decoding
#12 | 2012-05-31Reconfigurable encoding per multiple communications standards
#13 | 2012-05-31Branch metrics calculation for multiple communications standards
#14 | 2012-05-24L-value generation in a decoder
#15 | 2012-05-10No-delay microsequencer
#16 | 2012-03-01Reconfigurable BCH decoder
#17 | 2011-09-29Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards
#18 | 2010-11-25BCH or reed-solomon decoder with syndrome modification
#19 | 2010-11-04Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder
#20 | 2010-06-17Parallel true random number generator architecture
#21 | 2010-02-04Scheme for erasure locator polynomial calculation in error-and-erasure decoder
#22 | 2010-02-04System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors
#23 | 2009-06-18Configurable Reed-Solomon decoder based on modified Forney syndromes
#24 | 2008-06-26Low area architecture in BCH decoder
#25 | 2007-10-04Ramptime propagation on designs with cycles
#26 | 2007-04-26Method and apparatus for controlling congestion during integrated circuit design resynthesis
#27 | 2007-03-01Method of selecting cells in logic restructuring
#28 | 2006-06-08Ramptime propagation on designs with cycles
#29 | 2006-05-25Multiple buffer insertion in global routing
#30 | 2006-05-25Method of selecting cells in logic restructuring
#31 | 2006-03-02Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths
#32 | 2005-09-22Method and apparatus for performing logical transformations for global routing
#33 | 2005-05-26Process and apparatus for placement of megacells in ICs design
#34 | 2005-05-26Method and apparatus for finding optimal unification substitution for formulas in technology library
#35 | 2005-03-15Method to find boolean function symmetries
#36 | 2005-01-18Multidirectional router
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