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Inventor profile of:

David Abercrombie

City:

Gresham, Oregon

Country:

United States

Published Applications:

8

Last publication date:

2007-02-06

Top Assignees for applications by David Abercrombie

The entities that hold a legal rights for patent applications filed by inventor Abercrombie David:

  • LSI LOGIC CORPORATION 4 Milpitas, CA United States
  • LSI CORPORATION 4 Milpitas, CA United States

Recent patent applications by Abercrombie David

David Abercrombie from Gresham, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2007-02-06
US10135383
-

Method for analyzing manufacturing data

#2 | 2006-08-31
US20060191634A1
Electricity

Apparatus for wafer patterning to reduce edge exclusion zone

#3 | 2006-05-04
US20060094246A1
Electricity

Method of wafer patterning for reducing edge exclusion zone

#4 | 2005-12-27
US10334430
-

Optimization of die yield in a silicon wafer “sweet spot”

#5 | 2005-07-07
US20050145841A1
Electricity

Method to selectively identify reliability risk die based on characteristics of local regions on the wafer

#6 | 2005-06-16
US20050132308A1
Electricity

Method for calculating high-resolution wafer parameter profiles

#7 | 2005-04-12
US10454027
-

Method to selectively identify reliability risk die based on characteristics of local regions on the wafer

#8 | 2005-03-17
US20050060336A1
Physics

Method of isolating sources of variance in parametric data

InventorID:

4618647 ⎘

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