Inventor profile of:

Michael Alfano

City:

Austin, Texas

Country:

United States

Published Applications:

18

Last publication date:

2026-01-22

Top Assignees for applications by Michael Alfano

The entities that hold a legal rights for patent applications filed by inventor Alfano Michael:

Recent patent applications by Alfano Michael

Michael Alfano from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-22
US20260026360A1
Electricity

APPARATUS AND METHOD FOR IMPROVING YIELD OF ADVANCED PACKAGES

#2 | 2025-10-02
US20250309082A1
Electricity

Through Package Vertical Interconnect and Method of Making Same

#3 | 2025-09-18
US20250293133A1
Electricity

Through Package Vertical Interconnect and Method of Making Same

#4 | 2025-08-28
US20250273604A1
Electricity

Semiconductor Package with Integrated Capacitors

#5 | 2025-06-26
US20250210548A1
Electricity

EMBEDDED VOLTAGE REGULATION MODULE

#6 | 2025-01-09
US20250015019A1
Electricity

Semiconductor Package with Integrated Capacitors

#7 | 2024-10-10
US20240337799A1
Physics

Co-Packaging Assembly and Method for Attaching Photonic Dies/Modules to Multi-Chip Active/Passive Substrate

#8 | 2024-08-01
US20240258041A1
Electricity

Low-Equivalent-Series-Resistance Capacitors with Solid-State Current Collectors Using Conductive Inks

#9 | 2024-04-11
US20240120293A1
Electricity

Method and Apparatus for Prevention, Cessation, Detection, and Monitoring of Cracks in Substrates

#10 | 2023-12-21
US20230411174A1
Electricity

Package Assembly and Method of Attaching Multi-Height Dies/Modules to Multi-Chip Active/Passive Substrate

#11 | 2023-12-07
US20230395305A1
Electricity

Inductors Embedded in Package Substrate and Board and Method and System for Manufacturing the Same

#12 | 2023-10-26
US20230343687A1
Electricity

Through Package Vertical Interconnect and Method of Making Same

#13 | 2023-09-14
US20230290746A1
Electricity

Semiconductor package with integrated capacitors

#14 | 2013-12-26
US20130342231A1
Physics

SEMICONDUCTOR SUBSTRATE WITH ONBOARD TEST STRUCTURE

#15 | 2013-12-26
US20130341783A1
Electricity

Interposer with identification system

#16 | 2013-10-03
US20130256913A1
Electricity

DIE STACKING WITH COUPLED ELECTRICAL INTERCONNECTS TO ALIGN PROXIMITY INTERCONNECTS

#17 | 2013-10-03
US20130256895A1
Electricity

STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT

#18 | 2013-10-03
US20130256872A1
Electricity

Thermal management of stacked semiconductor chips with electrically non-functional interconnects

InventorID:

463214 ⎘