Michael J. Schulte

Selective Transfer of Cache Block Data

Flexible, scalable graph-processing accelerator

Multi-Stack Compute Chip and Memory Architecture

MULTI-DIE SYSTEM PERFORMANCE OPTIMIZATION

SYSTEMS AND METHODS FOR INTERPOLATING REGISTER-BASED LOOKUP TABLES

Flexible, scalable graph-processing accelerator

Multi-die system performance optimization

Distributed computing with phase change material thermal management

COMPUTING DEVICE WITH PHASE CHANGE MATERIAL THERMAL MANAGEMENT

Predicting power management state duration on a per-process basis and modifying cache size based on the predicted duration

Die-stacked memory device with reconfigurable logic

Configuring idle states for entities in a computing device based on predictions of durations of idle periods

PREDICTION FOR POWER GATING

Stacked semiconductor chip device with phase change material

Idle phase exit prediction

Power control for multi-core data processor

Idle Phase Prediction For Integrated Circuits

Computation memory operations in a logic layer of a stacked memory

Die-stacked memory device providing data translation

Write endurance management techniques in the logic layer of a stacked memory

Compound Memory Operations in a Logic Layer of a Stacked Memory

Processing engine for complex atomic operations

Cache coherency using die-stacked memory device with logic die

Die-stacked memory device with reconfigurable logic

Redundant Threading for Improved Reliability

Using a linear prediction to configure an idle state of an entity in a computing device

Method and apparatus for power reduction during lane divergence

Apparatus and Method for Fast Cache Shutdown