David A. Kaplan

Atomic Update Instructions with Bit Masking

Isolation-Based Confidentiality

Storing Indications of Cleared Cache Lines

Root-Trusted Guest Memory Page Management

Security Framework for Virtual Machines

Peripheral device protocols in confidential compute architectures

Split random number generator

Platform firmware isolation

Using return address predictor to speed up control stack return address verification

Controlling access by IO devices to pages in a memory in a computing device

Controlling access to pages in a memory in a computing device

System and method for virtualized process isolation including preventing a kernel from accessing user address space

Controlling access to pages in a memory in a computing device

Controlling access to pages in a memory in a computing device

KEY MANAGEMENT FOR SECURE MEMORY ADDRESS SPACES

Hypervisor post-write notification of control and debug register updates

Method for privileged mode based secure input mechanism

Cryptographic protection of information in a processing system

Unified store queue for reducing linear aliasing effects

Leveraging a peripheral device to execute a machine instruction

Promoting transactions hitting critical beat of cache line load requests

Allocating store queue entries to store instructions for early store-to-load forwarding

PAGE CROSS MISALIGN BUFFER

ELIGIBLE STORE MAPS FOR STORE-TO-LOAD FORWARDING

Hardware random number generator

Methods and apparatus related to processor sleep states

Hardware based return pointer encryption

RETURN ADDRESS TRACKING MECHANISM

AUTHENTICATING MICROCODE PATCHES WITH EXTERNAL ENCRYPTION ENGINE

LOAD/STORE PICKER

Speculative tablewalk promotion

Store replay policy

Interrupt virtualization

METHOD AND APPARATUS FOR GENERATING AN ENHANCED PROCESSOR RESYNC INDICATOR SIGNAL USING HASH FUNCTIONS AND A LOAD TRACKING UNIT

Programmable atomic memory using hardware validation agent

Programmable atomic memory using stored atomic procedures

Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator

Processor Configured to Virtualize Guest Local Interrupt Controller

Interrupt virtualization

CACHE SCRATCH-PAD AND METHOD THEREFOR

Early branch determination

Executing micro-code instruction with delay field and address of next instruction which is decoded after indicated delay

REGISTER REDUCTION AND LIVENESS ANALYSIS TECHNIQUES FOR PROGRAM CODE