Shaofeng YU

MOSFET with source side only stress

CMOS process to improve SRAM yield

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

Asymmetric static random access memory cell with dual stress liner

MOSFET with source side only stress

CMOS process to improve SRAM yield

Low cost transistors using gate orientation and optimized implants

Transistor gate electrode having conductor material layer

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

Gate dielectric first replacement gate processes and integrated circuits therefrom

Transistor gate electrode having conductor material layer

Low cost transistors using gate orientation and optimized implants

LOW COST SYMMETRIC TRANSISTORS

Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device

IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS

Method for integration of replacement gate in CMOS flow

Gate dielectric first replacement gate processes and integrated circuits therefrom

Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates

Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device

Transistor gate electrode having conductor material layer

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device

Method of forming source and drain regions utilizing dual capping layers and split thermal processes

Method of enhancing drive current in a transistor

PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT ETCH-STOP LINER LAYERS

DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS

FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN

Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device

Method of Forming a Fully Silicided Semiconductor Device with Independent Gate and Source/Drain Doping and Related Device

Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device

Fabrication of transistors with a fully silicided gate electrode and channel strain

Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes

Method of forming silicided gates using buried metal layers

Dual poly deposition and through gate oxide implants

Transistor gate electrode having conductor material layer

Process For Selectively Removing Dielectric Material in the Presence of Metal Silicide

Method for fabricating a transistor using a low temperature spike anneal

Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor

INTEGRATED CIRCUIT CONTAINING POLYSILICON GATE TRANSISTORS AND FULLY SILICIDIZED METAL GATE TRANSISTORS

Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors

Method to obtain fully silicided poly gate

Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors

Method for fabricating dual work function metal gates

Method for manufacturing a silicided gate electrode using a buffer layer

Method to improve SRAM performance and stability

Single metal gate material CMOS using strained si-silicon germanium heterojunction layered substrate

Semiconductor device having a fully silicided gate electrode and method of manufacture therefor

Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Transistor gate electrode having conductor material layer