Mohan Dunga

HOLE PRE-CHARGE FROM BITLINE SIDE TO ENABLE FULL REVERSE ORDER PROGRAM SUB-BLOCK MODE

HIGH BANDWIDTH NON-VOLATILE MEMORY

ERASE BIAS SCHEME TO LOWER VERAMAX AND NAND CHIP-SIZE SHRINK

THREE-DIMENSIONAL MEMORY DEVICE HAVING A COMPACT WORD LINE DRIVER TRANSISTOR LAYOUT

THREE-DIMENSIONAL MEMORY DEVICE HAVING A COMPACT WORD LINE DRIVER TRANSISTOR LAYOUT

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING OVERLYING THIN FILM TRANSISTOR CONTROL CIRCUIT AND METHOD OF MAKING THEREOF

UNSELECT WORD LINE SWITCH BIAS SCHEME FOR NON-VOLATILE MEMORY APPARATUS

THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PERIPHERAL CIRCUIT WITH FIN AND PLANAR FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF

Programming to minimize cross-temperature threshold voltage widening

Non-volatile memory with capacitors using metal under signal line or above a device capacitor

Non-volatile memory with capacitors using metal under signal line or above a device capacitor

Three-dimensional memory device containing multiple size drain contact via structures and method of making same

Concurrent multi-state program verify for non-volatile memory

Systems and methods for high-performance write operations

Non-volatile memory with pool capacitor

Non-volatile memory with pool capacitor

Non-volatile memory with capacitors using metal under signal line or above a device capacitor

Non-volatile memory with capacitors using metal under pads

System and method for in-situ programming and read operation adjustments in a non-volatile memory

Systems and methods for high-performance write operations

Metal contact via structure surrounded by an air gap and method of making thereof

System and method for string-based erase verify to create partial good blocks

Multiple liner interconnects for three dimensional memory devices and method of making thereof

System and method for programming a memory device with multiple writes without an intervening erase

Erase for partially programmed blocks in non-volatile memory

Erase speed based word line control

Cell current based bit line voltage

Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof

System solution for first read issue using time dependent read voltages

Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory

Smart verify for programming non-volatile memory

Non-volatile storage systems and methods

Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect

Controlling dummy word line bias during erase in non-volatile memory

Method and apparatus for program and erase of select gate transistors

Compensation for temperature dependence of bit line resistance

Method and apparatus for program and erase of select gate transistors

Pre-charge during programming for 3D memory using gate-induced drain leakage

Method and apparatus for program and erase of select gate transistors

Single-level cell endurance improvement with pre-defined blocks

Pre-charge during programming for 3D memory using gate-induced drain leakage

Method of forming PN floating gate non-volatile storage elements and transistor having N+ gate

Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory

P-/Metal floating gate non-volatile storage element

PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT