Inventor profile of:

Amol Joshi

City:

Sunnyvale, California

Country:

United States

Published Applications:

26

Last publication date:

2016-06-23

Top Assignees for applications by Amol Joshi

The entities that hold a legal rights for patent applications filed by inventor Joshi Amol:

Recent patent applications by Joshi Amol

Amol Joshi from Sunnyvale, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2016-06-23
US20160181380A1
Electricity

Semiconductor Device Metal-Insulator-Semiconductor Contacts with Interface Layers and Methods for Forming the Same

#2 | 2016-03-31
US20160093711A1
Electricity

Tantalum carbide metal gate stack for mid-gap work function applications

#3 | 2015-12-31
US20150380309A1
Electricity

Metal-insulator-semiconductor (MIS) contact with controlled defect density

#4 | 2015-10-29
US20150311206A1
Electricity

Gate structures for transistor devices for CMOS applications and products

#5 | 2015-07-02
US20150187664A1
Electricity

High Productivity Combinatorial Testing of Multiple Work Function Materials on the Same Semiconductor Substrate

#6 | 2015-05-21
US20150140838A1
Electricity

Two Step Deposition of High-k Gate Dielectric Materials

#7 | 2015-04-30
US20150118828A1
Electricity

Reduction of native oxides by annealing in reducing gas or plasma

#8 | 2015-04-02
US20150093914A1
Electricity

METHODS FOR DEPOSITING AN ALUMINUM OXIDE LAYER OVER GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS

#9 | 2015-04-02
US20150093889A1
Electricity

METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITS

#10 | 2015-04-02
US20150093887A1
Electricity

METHODS FOR REMOVING A NATIVE OXIDE LAYER FROM GERMANIUM SUSBTRATES IN THE FABRICATION OF INTEGRATED CIRCUITSI

#11 | 2015-03-05
US20150064361A1
Performing operations; transporting

UV treatment for ALD film densification

#12 | 2015-03-05
US20150061027A1
Electricity

Methods of forming gate structures for transistor devices for CMOS applications

#13 | 2014-10-23
US20140312409A1
Electricity

System and method for manufacturing self-aligned STI with single poly

#14 | 2014-06-26
US20140179100A1
Electricity

Method to control depth profiles of dopants using a remote plasma source

#15 | 2014-06-12
US20140162384A1
Electricity

PVD-ALD-CVD hybrid HPC for work function material screening

#16 | 2014-04-10
US20140099785A1
Electricity

Sacrificial Low Work Function Cap Layer

#17 | 2014-04-01
US13706680
-

Method for forming MOS capacitor

#18 | 2014-02-27
US20140055152A1
Physics

Circular transmission line methods compatible with combinatorial processing of semiconductors

#19 | 2014-02-04
US11639667
-

Self-aligned STI with single poly for manufacturing a flash memory device

#20 | 2014-01-09
US20140008763A1
Electricity

DISTRIBUTED SUBSTRATE TOP CONTACT FOR MOSCAP MEASUREMENTS

#21 | 2013-11-28
US20130316472A1
Electricity

High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction

#22 | 2011-07-21
US20110175158A1
Electricity

Dual charge storage node memory device and methods for fabricating such device

#23 | 2011-03-29
US11408866
-

Dual charge storage node memory device and methods for fabricating such device

#24 | 2008-12-25
US20080315290A1
Electricity

Memory device and methods for its fabrication

#25 | 2008-10-07
US11409361
-

Memory device and methods for its fabrication

#26 | 2008-04-03
US20080079061A1
Electricity

Flash memory cell structure for increased program speed and erase speed

InventorID:

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