Toronto
Canada
56
2026-05-28
The entities that hold a legal rights for patent applications filed by inventor Bajic Ljubisa:
Ljubisa Bajic from Toronto, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
MASK PROGRAMMABLE ROM USING SHARED CONNECTIONS
#2 | 2026-02-26INTEGRATED CIRCUIT WITH FINE TUNING MODEL PARAMETERS FOR NOISY MEMORY CANCELLATION
#3 | 2026-02-12PROCESSING CORE WITH METADATA ACTUATED CONDITIONAL GRAPH EXECUTION
#4 | 2026-01-22HARDWARE IMPLEMENTED CODEBOOK POINTERS
#5 | 2025-10-09SEAMLESS PLACE AND ROUTE FOR HETEROGENEOUS NETWORK OF PROCESSOR CORES
#6 | 2025-10-02Software Managed Cache with Hardware Optimization
#7 | 2025-07-31OVERLAY LAYER FOR NETWORK OF PROCESSOR CORES
#8 | 2025-07-24COMPUTING ARCHITECTURE WITH MODEL CORE AND FINE-TUNING PORTION
#9 | 2025-07-10LARGE PARAMETER SET COMPUTATION ACCELERATOR USING MEMORY WITH PARAMETER ENCODING
#10 | 2025-04-17Large Parameter Set Computation Accelerator Using Configurable Connectivity Mesh
#11 | 2025-01-23INTEGRATED RANDOM ACCESS MEMORY USING INVERTER LOOPS
#12 | 2025-01-23Multibit High Density Read Only Memory Using Multiple Reference Biases
#13 | 2025-01-23Integrated Denoising Neural Network for High Density Memory
#14 | 2024-10-17PROCESSING CORE WITH METADATA ACTUATED CONDITIONAL GRAPH EXECUTION
#15 | 2024-10-10PROCESSING CORE WITH DATA ASSOCIATIVE ADAPTIVE ROUNDING
#16 | 2024-09-26SEAMLESS PLACE AND ROUTE FOR HETEROGENEOUS NETWORK OF PROCESSOR CORES
#17 | 2024-04-04MULTIPLICATION HARDWARE BLOCK WITH ADAPTIVE FIDELITY CONTROL SYSTEM
#18 | 2023-10-12Seamless place and route for heterogenous network of processor cores
#19 | 2023-10-12Sparsity uniformity enforcement for multicore processor
#20 | 2023-09-07Overlay layer hardware unit for network of processor cores
#21 | 2023-08-17RUNTIME PREDICTORS FOR COMPUTATION REDUCTION IN DEPENDENT COMPUTATIONS
#22 | 2023-08-03Processing core with data associative adaptive rounding
#23 | 2023-07-27Processor cores using content object identifiers for routing and computation
#24 | 2023-06-22RUNTIME PREDICTORS FOR NEURAL NETWORK COMPUTATION REDUCTION
#25 | 2023-06-08Computational circuit with hierarchical accumulator
#26 | 2023-05-11Sparsity uniformity enforcement for multicore processor
#27 | 2023-05-11Sparsity uniformity enforcement for multicore processor
#28 | 2023-03-02Data structure optimized dedicated memory caches
#29 | 2023-02-09Overlay layer for network of processor cores
#30 | 2022-10-06Graph execution using access request response dynamic batch assembly
#31 | 2022-10-06Data structure optimized dedicated memory caches
#32 | 2022-08-04Application data flow graph execution using network-on-chip overlay
#33 | 2022-07-14PROCESSING CORE WITH OPERATION SUPPRESSION BASED ON CONTRIBUTION ESTIMATE
#34 | 2022-06-16Processor cores using packet identifiers for routing and computation
#35 | 2022-03-31Overlay layer hardware unit for network of processor cores
#36 | 2021-12-09PROCESSING CORE WITH METADATA ACTUATED CONDITIONAL GRAPH EXECUTION
#37 | 2021-11-25Speculative resource allocation for routing on interconnect fabrics
#38 | 2021-09-02Processing core with data associative adaptive rounding
#39 | 2021-02-11Processing core with meta data actuated conditional graph execution
#40 | 2021-02-04Overlay layer for network of processor cores
#41 | 2020-12-24Processor cores using packet identifiers for routing and computation
#42 | 2020-07-30Processing core data compression and storage system
#43 | 2020-06-04Processing core with operation suppression based on contribution estimate
#44 | 2020-04-02Processing core with data associative adaptive rounding
#45 | 2019-12-12Processing core data compression and storage system
#46 | 2019-09-05Processing core with operation suppression based on contribution estimate
#47 | 2019-02-14Processing core with metadata actuated conditional graph execution
#48 | 2018-11-15Processing core with operation suppression based on contribution estimate
#49 | 2018-11-01Processing core with metadata actuated conditional graph execution
#50 | 2018-10-11CONDITIONAL GRAPH EXECUTION BASED ON PRIOR SIMPLIFIED GRAPH EXECUTION
#51 | 2018-06-28Adaptive oscillator for clock generation
#52 | 2017-12-28SYSTEM AND METHOD FOR USING VIRTUAL VECTOR REGISTER FILES
#53 | 2013-10-17Processor bridge power management
#54 | 2013-06-20Apparatus and method for managing power among a plurality of processors sharing a thermal platform
#55 | 2013-01-24Dynamic weight calculation in a digital power estimation and management system
#56 | 2007-09-06Dynamically controlled power reduction method and circuit for a graphics processor
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