Inventor profile of:

Benjamin T. Sander

City:

Austin, Texas

Country:

United States

Published Applications:

29

Last publication date:

2026-01-22

Top Assignees for applications by Benjamin T. Sander

The entities that hold a legal rights for patent applications filed by inventor Sander Benjamin T.:

Recent patent applications by Sander Benjamin T.

Benjamin T. Sander from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-22
US20260023754A1
Physics

CONTENT ADAPTIVE DATA ARRAY WITH A SHARED SCALE AND TYPE SELECTOR BIT

#2 | 2025-06-12
US20250190813A1
Physics

FINE-TUNING OF NEURAL NETWORKS

#3 | 2022-08-25
US20220269620A1
Physics

Access log and address translation log for a processor

#4 | 2017-06-29
US20170185514A1
Physics

Caching policies for processing units on multiple sockets

#5 | 2017-03-23
US20170083455A1
Physics

Cache access statistics accumulation for cache line replacement selection

#6 | 2017-03-23
US20170083240A1
Physics

Selective data copying between memory modules

#7 | 2016-12-29
US20160378682A1
Physics

Access log and address translation log for a processor

#8 | 2016-12-29
US20160378674A1
Physics

Shared virtual address space for heterogeneous processors

#9 | 2016-03-31
US20160092181A1
Physics

Automatic source code generation for accelerated function calls

#10 | 2013-12-19
US20130339978A1
Physics

LOAD BALANCING FOR HETEROGENEOUS SYSTEMS

#11 | 2012-01-26
US20120023314A1
Physics

PAIRED EXECUTION SCHEDULING OF DEPENDENT MICRO-OPERATIONS

#12 | 2011-05-03
US10839471
-

System and method for scheduling operations using speculative data operands

#13 | 2011-03-17
US20110066811A1
Physics

Store aware prefetching for a datastream

#14 | 2010-07-22
US20100185820A1
Physics

Processor power management and method

#15 | 2008-09-25
US20080235491A1
Physics

Determination of current stack pointer value using architectural and speculative stack pointer delta values

#16 | 2008-06-12
US20080141008A1
Physics

EXECUTION ENGINE MONITORING DEVICE AND METHOD THEREOF

#17 | 2008-06-12
US20080141002A1
Physics

INSTRUCTION PIPELINE MONITORING DEVICE AND METHOD THEREOF

#18 | 2008-06-12
US20080140993A1
Physics

FETCH ENGINE MONITORING DEVICE AND METHOD THEREOF

#19 | 2008-05-13
US10755692
-

Controlling writes to non-renamed register space in an out-of-order execution microprocessor

#20 | 2008-04-22
US10429082
-

System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

#21 | 2008-01-01
US10679745
-

Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots

#22 | 2007-09-04
US10429159
-

Speculation pointers to identify data-speculative operations in microprocessor

#23 | 2007-03-27
US10822468
-

Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation

#24 | 2007-01-16
US10458457
-

Load store unit with replay mechanism

#25 | 2006-11-07
US10320034
-

Dynamic page conflict prediction for DRAM

#26 | 2005-12-06
US10037403
-

Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction

#27 | 2005-11-10
US20050247774A1
Physics

System and method for validating a memory file that links speculative results of load operations to register values

#28 | 2005-09-27
US10229563
-

Scheduler for use in a microprocessor that supports data-speculative execution

#29 | 2005-04-07
US20050076180A1
Physics

System and method for handling exceptional instructions in a trace cache based processor

InventorID:

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