Inventor profile of:

John M. King

City:

Austin, Texas

Country:

United States

Published Applications:

24

Last publication date:

2026-01-01

Top Assignees for applications by John M. King

The entities that hold a legal rights for patent applications filed by inventor King John M.:

Recent patent applications by King John M.

John M. King from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-01-01
US20260003807A1
Physics

Variable Access Latency with Storage Array Extensions on Stacked Dies

#2 | 2025-09-11
US20250284497A1
Physics

SYSTEMS AND METHODS FOR TRACKING OUT-OF-ORDER LOAD OPERATIONS WITH CHECKPOINT BITS OF DATA CACHE TAGS

#3 | 2024-10-03
US20240330185A1
Physics

Pseudo out-of-order store commit

#4 | 2024-08-27
US17855681
Physics

Systems and methods for tracking data cache miss requests with data cache tags

#5 | 2022-03-31
US20220100662A1
Physics

Techniques for handling cache coherency traffic for contended semaphores

#6 | 2021-05-27
US20210157590A1
Physics

Techniques for performing store-to-load forwarding

#7 | 2021-04-01
US20210096858A1
Physics

Multi-modal gather operation

#8 | 2021-04-01
US20210096857A1
Physics

Masked multi-lane instruction memory fault handling using fast and slow execution paths

#9 | 2019-06-20
US20190187990A1
Physics

System and method for a lightweight fencing operation

#10 | 2019-06-06
US20190171452A1
Physics

System and method for load fusion

#11 | 2019-05-30
US20190163475A1
Physics

System and method for store fusion

#12 | 2019-05-30
US20190163471A1
Physics

System and method for processing a load micro-operation by allocating an address generation scheduler queue entry without allocating a load queue entry

#13 | 2018-06-28
US20180181496A1
Physics

Configurable skewed associativity in a translation lookaside buffer

#14 | 2018-03-22
US20180081810A1
Physics

Techniques for handling cache coherency traffic for contended semaphores

#15 | 2018-03-22
US20180081544A1
Physics

Lock address contention predictor

#16 | 2018-03-15
US20180074977A1
Physics

Speculative retirement of post-lock instructions

#17 | 2018-02-15
US20180046583A1
Physics

Updating least-recently-used data for greater persistence of higher generality cache entries

#18 | 2018-02-15
US20180046463A1
Physics

System and method for load and store queue allocations at address generation time

#19 | 2015-04-30
US20150121010A1
Physics

Unified store queue for reducing linear aliasing effects

#20 | 2014-08-28
US20140244978A1
Physics

Checkpointing registers for transactional memory

#21 | 2014-05-08
US20140129804A1
Physics

TRACKING AND RECLAIMING PHYSICAL REGISTERS

#22 | 2014-03-06
US20140068175A1
Physics

Oldest operation translation look-aside buffer

#23 | 2013-12-26
US20130346694A1
Physics

Method and apparatus including a probe filter for shared caches utilizing inclusion bits and a victim probe bit

#24 | 2012-02-09
US20120036342A1
Physics

Lane crossing instruction selecting operand data bits conveyed from register via direct path and lane crossing path for execution

InventorID:

590007 ⎘