Austin, Texas
United States
24
2026-01-01
The entities that hold a legal rights for patent applications filed by inventor King John M.:
John M. King from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Variable Access Latency with Storage Array Extensions on Stacked Dies
#2 | 2025-09-11SYSTEMS AND METHODS FOR TRACKING OUT-OF-ORDER LOAD OPERATIONS WITH CHECKPOINT BITS OF DATA CACHE TAGS
#3 | 2024-10-03Pseudo out-of-order store commit
#4 | 2024-08-27Systems and methods for tracking data cache miss requests with data cache tags
#5 | 2022-03-31Techniques for handling cache coherency traffic for contended semaphores
#6 | 2021-05-27Techniques for performing store-to-load forwarding
#7 | 2021-04-01Multi-modal gather operation
#8 | 2021-04-01Masked multi-lane instruction memory fault handling using fast and slow execution paths
#9 | 2019-06-20System and method for a lightweight fencing operation
#10 | 2019-06-06System and method for load fusion
#11 | 2019-05-30System and method for store fusion
#12 | 2019-05-30System and method for processing a load micro-operation by allocating an address generation scheduler queue entry without allocating a load queue entry
#13 | 2018-06-28Configurable skewed associativity in a translation lookaside buffer
#14 | 2018-03-22Techniques for handling cache coherency traffic for contended semaphores
#15 | 2018-03-22Lock address contention predictor
#16 | 2018-03-15Speculative retirement of post-lock instructions
#17 | 2018-02-15Updating least-recently-used data for greater persistence of higher generality cache entries
#18 | 2018-02-15System and method for load and store queue allocations at address generation time
#19 | 2015-04-30Unified store queue for reducing linear aliasing effects
#20 | 2014-08-28Checkpointing registers for transactional memory
#21 | 2014-05-08TRACKING AND RECLAIMING PHYSICAL REGISTERS
#22 | 2014-03-06Oldest operation translation look-aside buffer
#23 | 2013-12-26Method and apparatus including a probe filter for shared caches utilizing inclusion bits and a victim probe bit
#24 | 2012-02-09Lane crossing instruction selecting operand data bits conveyed from register via direct path and lane crossing path for execution
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