Inventor profile of:

Meng Ding

City:

Sunnyvale, California

Country:

United States

Published Applications:

25

Last publication date:

2020-04-14

Top Assignees for applications by Meng Ding

The entities that hold a legal rights for patent applications filed by inventor Ding Meng:

Recent patent applications by Ding Meng

Meng Ding from Sunnyvale, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-04-14
US14865563
Electricity

System and method for manufacturing self-aligned STI with single poly

#2 | 2014-10-23
US20140312409A1
Electricity

System and method for manufacturing self-aligned STI with single poly

#3 | 2014-03-06
US20140061771A1
Electricity

Memory Device with Charge Trap

#4 | 2014-02-04
US11639667
-

Self-aligned STI with single poly for manufacturing a flash memory device

#5 | 2010-02-04
US20100027350A1
Physics

Flash memory programming and verification with reduced leakage current

#6 | 2009-05-26
US11416703
-

Two-bit memory cell having conductive charge storage segments and method for fabricating same

#7 | 2008-12-25
US20080315290A1
Electricity

Memory device and methods for its fabrication

#8 | 2008-10-07
US11409361
-

Memory device and methods for its fabrication

#9 | 2008-06-26
US20080151634A1
Physics

Negative wordline bias for reduction of leakage current during flash memory operation

#10 | 2008-06-26
US20080150011A1
Electricity

INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM

#11 | 2008-06-26
US20080150005A1
Electricity

MEMORY SYSTEM WITH DEPLETION GATE

#12 | 2008-06-26
US20080150000A1
Electricity

MEMORY SYSTEM WITH SELECT GATE ERASE

#13 | 2008-04-10
US20080083946A1
Electricity

Memory cell system with charge trap

#14 | 2008-04-03
US20080079061A1
Electricity

Flash memory cell structure for increased program speed and erase speed

#15 | 2008-03-04
US11416551
-

Method for determining wordline critical dimension in a memory array and related structure

#16 | 2008-02-07
US20080032475A1
Electricity

MEMORY CELL SYSTEM WITH GRADIENT CHARGE ISOLATION

#17 | 2008-02-07
US20080032464A1
Electricity

MEMORY CELL SYSTEM WITH NITRIDE CHARGE ISOLATION

#18 | 2008-01-31
US20080023750A1
Electricity

Memory cell system with multiple nitride layers

#19 | 2008-01-17
US20080012060A1
Electricity

Memory cell system with charge trap

#20 | 2007-10-25
US20070247924A1
Physics

Methods for erasing memory devices and multi-level programming memory device

#21 | 2007-10-25
US20070247923A1
Electricity

Methods for erasing and programming memory devices

#22 | 2007-10-11
US20070237003A1
Physics

Flash memory programming and verification with reduced leakage current

#23 | 2007-09-20
US20070215932A1
Electricity

Memory cell system using silicon-rich nitride

#24 | 2006-11-30
US20060268593A1
Physics

Read-only memory array with dielectric breakdown programmability

#25 | 2006-09-07
US20060196040A1
Performing operations; transporting

Method for making a magnetoresistive read head having a pinned layer width greater than the free layer stripe height

InventorID:

672213 ⎘