Stefan Flachowsky

Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof

NVM device in SOI technology and method of fabricating an according device

Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof

SEMICONDUCTOR DEVICE AND METHOD

Semiconductor structure including a first transistor and a second transistor

Method including a formation of a transistor and semiconductor structure including a first transistor and a second transistor

Ferroelectric FinFET

CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH

DENSELY PACKED TRANSISTOR DEVICES

Three-dimensional transistor with improved channel mobility

Method of forming a device including a floating gate electrode and a layer of ferroelectric material

Ferroelectric FinFET

Integrated circuits with fets having nanowires and methods of manufacturing the same

Methods of forming a complex GAA FET device at advanced technology nodes

DEVICES WITH FULLY AND PARTIALLY SILICIDED GATE STRUCTURES IN GATE FIRST CMOS TECHNOLOGIES

Method of forming a semiconductor device structure and such a semiconductor device structure

MEANDER RESISTOR

Efficient main spacer pull back process for advanced VLSI CMOS technologies

Multi-gate FETs having corrugated semiconductor stacks and method of forming the same

METHOD INCLUDING A REPLACEMENT OF A DUMMY GATE STRUCTURE WITH A GATE STRUCTURE INCLUDING A FERROELECTRIC MATERIAL

Highly conformal extension doping in advanced multi-gate devices

FINFET doping method with curvilnear trajectory implantation beam path

Methods of making integrated circuits and components thereof

DEVICE INCLUDING A FLOATING GATE ELECTRODE AND A LAYER OF FERROELECTRIC MATERIAL AND METHOD FOR THE FORMATION THEREOF

Selective FuSi gate formation in gate first CMOS technologies

Temperature independent resistor

Forming transistors without spacers and resulting devices

FORMING A VERTICAL CAPACITOR AND RESULTING DEVICE

INTEGRATED CIRCUITS HAVING IMPROVED CONTACTS AND METHODS FOR FABRICATING SAME

Transistor with embedded stress-inducing layers

INTEGRATED CIRCUIT INCLUDING A SEMICONDUCTOR-ON-INSULATOR REGION AND A BULK REGION

Transistor devices with high-k insulation layers

Integrated circuits and methods for operating integrated circuits with non-volatile memory

MEANDER RESISTOR

Integrated inductor

Method for a uniform compressive strain layer and device thereof

ULTRATHIN BODY FULLY DEPLETED SILICON-ON-INSULATOR INTEGRATED CIRCUITS AND METHODS FOR FABRICATING SAME

LOW LEAKAGE PMOS TRANSISTOR

FIELD EFFECT TRANSISTORS FOR HIGH-PERFORMANCE AND LOW-POWER APPLICATIONS

E-fuse design for high-K metal-gate technology

SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR HAVING A LOW DOPED DRIFT REGION AND METHOD FOR THE FORMATION THEREOF

Sandwich silicidation for fully silicided gate formation

Transistor including a gate electrode extending all around one or more channel regions

Methods of forming a nanowire transistor device

Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof

Three-dimensional transistor with improved channel mobility

Simplified gate-first HKMG manufacturing flow

LATE IN-SITU DOPED SIGE JUNCTIONS FOR PMOS DEVICES ON 28 NM LOW POWER/HIGH PERFORMANCE TECHNOLOGIES USING A SILICON OXIDE ENCAPSULATION, EARLY HALO AND EXTENSION IMPLANTATIONS

Fully silicided gate formed according to the gate-first HKMG approach

Highly conformal extension doping in advanced multi-gate devices

Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer

Device including a transistor having a stressed channel region and method for the formation thereof

Spacer stress relaxation

Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby

Silicidation of semiconductor devices

Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages

Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection

Integrated circuits and methods for operating integrated circuits with non-volatile memory

Methods of removing gate cap layers in CMOS applications

Method for forming a semiconductor device and semiconductor device structures

Transistor including a gate electrode extending all around one or more channel regions

Contact geometry having a gate silicon length decoupled from a transistor length

STRESS MEMORIZATION TECHNIQUE

Channel SiGe removal from PFET source/drain region for improved silicide formation in HKMG technologies without embedded SiGe

TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES FORMED IN A SILICON/GERMANIUM SUBSTRATE

Methods of inducing a desired stress in the channel region of a transistor by performing ion implantation/anneal processes on the gate electrode

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Method of forming a semiconductor structure including a vertical nanowire

Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Canyon gate transistor and methods for its fabrication

SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE

Semiconductor device structure and methods for forming a CMOS integrated circuit structure

Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof

Source and drain doping using doped raised source and drain regions

THREE-DIMENSIONAL SILICON-BASED TRANSISTOR COMPRISING A HIGH-MOBILITY CHANNEL FORMED BY NON-MASKED EPITAXY

INTEGRATED CIRCUITS HAVING BORON-DOPED SILICON GERMANIUM CHANNELS AND METHODS FOR FABRICATING THE SAME

Integrated circuits with improved spacers and methods for fabricating same

METHODS FOR FABRICATING HIGH CARRIER MOBILITY FINFET STRUCTURES

Methods of forming transistor devices with high-k insulation layers and the resulting devices

Threshold voltage adjustment in a fin transistor by corner implantation

Stress enhanced CMOS circuits and methods for their manufacture

Replacement gate FinFET structures with high mobility channel

Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same

SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask

Methods of performing highly tilted halo implantation processes on semiconductor devices

Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Late in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations

Full silicidation prevention via dual nickel deposition approach

Semiconductor device with strain-inducing regions and method thereof

Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers

METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING RAISED DRAIN AND SOURCE REGIONS AND CORRESPONDING SEMICONDUCTOR DEVICE

Integrated circuits having protruding source and drain regions and methods for forming integrated circuits

Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers

Methods for fabricating integrated circuits having substrate contacts and integrated circuits having substrate contacts

METHODS OF FORMING FEATURES ON AN INTEGRATED CIRCUIT PRODUCT USING A NOVEL COMPOUND SIDEWALL IMAGE TRANSFER TECHNIQUE

METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH REDUCED ELECTRICAL PARAMETER VARIATION

Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts

Methods for fabricating MOS devices with stress memorization

Semiconductor devices having encapsulated stressor regions and related fabrication methods