Pete D. Vogt

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

Stacked memory with interface providing offset interconnects

Extended platform with additional memory module slots per CPU socket and configured for increased performance

Techniques to access or operate a dual in-line memory module via multiple data channels

HETEROGENEOUS MEMORY DIE STACKING FOR ENERGY EFFICIENT COMPUTING

Extended platform with additional memory module slots per CPU socket

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems

Extended platform with additional memory module slots per CPU socket and configured for increased performance

Extended application of error checking and correction code in memory

Remote memory operations

Extended platform with additional memory module slots per CPU socket

WRITE DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL

MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL

Read delivery for memory subsystem with narrow bandwidth repeater channel

Techniques to access or operate a dual in-line memory module via multiple data channels

MEMORY BROADCAST COMMAND

Memory channel having deskew separate from redrive

Embedded ECC address mapping

Apparatus and method to reduce power delivery noise for partial writes

Heterogeneous memory die stacking for energy efficient computing

Method, system and apparatus for evaluation of input/output buffer circuitry

Disabling outbound drivers for a last memory buffer on a memory channel

Memory channel having deskew separate from redrive

Memory channel having deskew separate from redrive

Disabling outbound drivers for a last memory buffer on a memory channel

Disabling outbound drivers for a last memory buffer on a memory channel

Memory channel with bit lane fail-over

Memory channel with bit lane fail-over

Training pattern for a biased clock recovery tracking loop

METHOD AND APPARATUS FOR MEMORY COMPRESSION

Memory channel with bit lane fail-over

Memory channel with redundant presence detect

Synchronized memory channels with unidirectional links

Embedded heat spreader

Memory channel with unidirectional links

Memory channel utilizing permuting status patterns

Memory channel with hot add/remove

Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems

Memory channel response scheduling

Memory channel with unidirectional links

Memory device identification

Memory single-to-multi load repeater architecture

Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal

Combined command and data code

Set partitioning for cache memories

Memory modules that receive clock information and are placed in a low power state

I/O data interconnect reuse as repeater

Embedded heat spreader

Memory transaction burst operation and memory components supporting temporally multiplexed error correction coding

Method, apparatus, and system for memory read transaction biasing in mirrored mode to provide thermal management

Training pattern for a biased clock recovery tracking loop

Method and apparatus for memory compression

Method and apparatus for increased memory bandwidth

Memory agent core clock aligned to lane

Memory channel with frame misalignment

Memory control translators

Early CRC delivery for partial frame

Data accumulation between data path having redrive circuit and memory device

Buffered memory module with implicit to explicit memory command expansion

Check codes mapped across multiple frames

Lane testing with variable mapping