Torsten Partsch

INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY

Memory component with programmable data-to-clock ratio

BUFFERED DYNAMIC RANDOM ACCESS MEMORY DEVICE

STACKED MEMORY DEVICE WITH INTERFACE DIE

Systems and Methods with Concurrent Link-Timing Calibration

LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH DEDICATED READ-WRITE DATA PATHS

Memory component with input/output data rate alignment

DRAM REFRESH CONTROL WITH MASTER WORDLINE GRANULARITY OF REFRESH INTERVALS

DATA DESTRUCTION

DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING

QUAD-CHANNEL DRAM

Low power memory control with on-demand bandwidth boost

ROW HAMMER MITIGATION

Data-buffer controller/control-signal redriver

Data destruction

RELIABILITY FOR DRAM DEVICE STACK

Interconnect based address mapping for improved reliability

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

Buffered dynamic random access memory device

Joint command dynamic random access memory (DRAM) apparatus and methods

Low power memory with on-demand bandwidth boost

Quad-channel DRAM

DRAM security erase

Memory component with input/output data rate alignment

Multi-chip package and interposer with signal line compression