Robert C. Wong

TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RANDOM ACCESS MEMORY (SRAM) AND DENSE LOGIC

TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RANDOM ACCESS MEMORY (SRAM) AND DENSE LOGIC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

Buried contact to provide reduced VFET feature-to-feature tolerance requirements

Buried contact to provide reduced VFET feature-to-feature tolerance requirements

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

Integrated circuit design layout optimizer based on process variation and failure mechanism

Stable and reliable FinFET SRAM with improved beta ratio

Stable and reliable FinFET SRAM with improved beta ratio

SRAM design to facilitate single fin cut in double sidewall image transfer process

SRAM design to facilitate single fin cut in double sidewall image transfer process

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures

SRAM cell with dynamic split ground and split wordline

SRAM cell with dynamic split ground and split wordline

TEST STRUCTURE AND METHOD OF TESTING A MICROCHIP

FinFET device

Cross-coupling of gate conductor line and active region in semiconductor devices

FinFET device

Cross-coupling of gate conductor line and active region in semiconductor devices

Semiconductor transistors having reduced distances between gate electrode regions

Boost cell supply write assist

Generation of metal holes by via mutation

Programmable PN anti-fuse

Structure and method for improved SRAM interconnect

SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function

SRAM cell design to improve stability

Circuit design

Design structure for SRAM active write assist for improved operational margins

High density SRAM cell with hybrid devices

Integration scheme for multiple metal gate work function structures

FINFET MEMORY DEVICE WITH DUAL SEPARATE GATES AND METHOD OF OPERATION

One-transistor static random access memory with integrated vertical PNPN device

SRAM active write assist method for improved operational margins

SRAM having active write assist for improved operational margins

FINFET STRUCTURE INCLUDING MULTIPLE SEMICONDUCTOR FIN CHANNEL HEIGHTS

Semiconductor transistors having reduced distances between gate electrode regions

Partially gated FINFET with gate dielectric on only one sidewall

SRAM voltage control for improved operational margins

One-transistor static random access memory with integrated vertical PNPN device

SRAM cell design to improve stability

STRUCTURES AND METHODS FOR FORMING SRAM CELLS WITH SELF-ALIGNED CONTACTS

Real-time adaptive SRAM array for high SEU immunity

SINGLE STRESS LINER FOR MIGRATION STABILITY AND SPEED

SRAM voltage control for improved operational margins

Method of producing a semiconductor interconnect architecture including generation of metal holes by via mutation

Discriminative SOI with oxide holes underneath DC source/drain

Generation of metal holes by via mutation

Secure and static 4T SRAM cells in EDRAM technology

Dense SRAM cells with selective SOI

SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD