Nepean
Canada
22
2022-12-22
The entities that hold a legal rights for patent applications filed by inventor Takefman Michael L.:
Michael L. Takefman from Nepean, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
System and method of interfacing co-processors and input/output devices via a main memory system
#2 | 2021-12-30System and method for providing a configurable timing control for a memory system
#3 | 2021-10-14System and method of interfacing co-processors and input/output devices via a main memory system
#4 | 2021-01-14System and method of interfacing co-processors and input/output devices via a main memory system
#5 | 2021-01-07System and method for implementing a multi-threaded device driver in a computer system
#6 | 2020-08-20System and method for providing a configurable timing control for a memory system
#7 | 2019-07-11System and method of interfacing co-processors and input/output devices via a main memory system
#8 | 2019-02-28System and method for implementing a multi-threaded device driver in a computer system
#9 | 2019-02-07System and method for providing a configurable timing control for a memory system
#10 | 2016-12-29System and method of interfacing co-processors and input/output devices via a main memory system
#11 | 2016-12-22SYSTEM AND METHOD FOR OFFSETTING THE DATA BUFFER LATENCY OF A DEVICE IMPLEMENTING A JEDEC STANDARD DDR-4 LRDIMM CHIPSET
#12 | 2015-12-03SYSTEM AND METHOD FOR BOOTING FROM A NON-VOLATILE MEMORY
#13 | 2015-11-12SYSTEM AND METHOD OF ACCESSING AND CONTROLLING A CO-PROCESSOR AND/OR INPUT/OUTPUT DEVICE VIA REMOTE DIRECT MEMORY ACCESS
#14 | 2015-11-12SYSTEM AND METHOD OF IMPLEMENTING AN OBJECT STORAGE DEVICE ON A COMPUTER MAIN MEMORY SYSTEM
#15 | 2015-10-29SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM
#16 | 2015-10-29System and method of interfacing co-processors and input/output devices via a main memory system
#17 | 2015-10-15System and method for offsetting the data buffer latency of a device implementing a JEDEC standard DDR-4 LRDIMM chipset
#18 | 2014-08-21System and method for providing a command buffer in a memory system
#19 | 2014-08-21System and method for unlocking additional functions of a module
#20 | 2014-08-21System and method for providing an address cache for memory map learning
#21 | 2014-08-07System and method of interfacing co-processors and input/output devices via a main memory system
#22 | 2012-08-09System and method of interfacing co-processors and input/output devices via a main memory system
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