Stuart A. Sieg

ALTERNATING HARDMASKS FOR TIGHT-PITCH LINE FORMATION

Alternating hardmasks for tight-pitch line formation

Alternating hardmasks for tight-pitch line formation

Fin field effect transistor devices with self-aligned gates

Alternating hardmasks for tight-pitch line formation

Semiconductor Fin Length Variability Control

Controlling fin hardmask cut profile using a sacrificial epitaxial structure

Fin cut profile using fin base liner

Approach to prevent collapse of high aspect ratio Fin structures for vertical transport Fin field effect transistor devices

Controlling gate length of vertical transistors

ALTERNATING HARD MASK FOR TIGHT-PITCH FIN FORMATION

Tunable hardmask for overlayer metrology contrast

Semiconductor fin length variability control

INVERSE TONE DIRECT PRINT EUV LITHOGRAPHY ENABLED BY SELECTIVE MATERIAL DEPOSITION

Alternating hardmasks for tight-pitch line formation

Vertical transport devices with greater density through modified well shapes

Measuring and modeling material planarization performance

Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows

Verifying planarization performance using electrical measures

Self-aligned double patterning formed fincut

Tunable hardmask for overlayer metrology contrast

Vertical transistors having improved gate length control using uniformly deposited spacers

Inverse tone direct print EUV lithography enabled by selective material deposition

Vertical transistors having multiple gate thicknesses for optimizing performance and device density

Vertical transistors having multiple gate thicknesses for optimizing performance and device density

Direct gate patterning for vertical transport field effect transistor

Alternating hardmasks for tight-pitch line formation

Registration mark formation during sidewall image transfer process

Alternating hardmasks for tight-pitch line formation

Alternating hardmasks for tight-pitch line formation

Alternating hardmasks for tight-pitch line formation

Margin for fin cut using self-aligned triple patterning

Vertical transistor with variable gate length

Stress retention in fins of fin field-effect transistors

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Margin for fin cut using self-aligned triple patterning

Structure and process to tuck fin tips self-aligned to gates

Structure and process to tuck fin tips self-aligned to gates

Registration mark formation during sidewall image transfer process

Gate cut on a vertical field effect transistor with a defined-width inorganic mask

Methods to control fin tip placement

Stress retention in fins of fin field-effect transistors

Cutting fins and gates in CMOS devices

Pitch scalable active area patterning structure and process for multi-channel fin FET technologies

Stress retention in fins of fin field-effect transistors

Gate cutting for a vertical transistor device

Pitch scalable active area patterning structure and process for multi-channel finFET technologies

Strained finFET device fabrication

Strained finFET device fabrication

Strained FinFET device fabrication

Strained finFET device fabrication

Registration mark formation during sidewall image transfer process

Structure and process to tuck fin tips self-aligned to gates

Strained finFET device fabrication

Registration mark formation during sidewall image transfer process

Self-aligned quadruple patterning process

Self-aligned quadruple patterning process

Patterning assist feature to mitigate reactive ion etch microloading effect

Selectively grown self-aligned fins for deep isolation integration

finFET isolation by selective cyclic etch

Front side wafer ID processing