Hayward, California
United States
29
2014-03-27
The entities that hold a legal rights for patent applications filed by inventor Tetelbaum Alexander:
Alexander Tetelbaum from Hayward, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Circuit Timing Analysis Incorporating the Effects of Temperature Inversion
#2 | 2013-02-21Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
#3 | 2012-11-01Timing error sampling generator and a method of timing testing
#4 | 2012-08-16Circuit timing analysis incorporating the effects of temperature inversion
#5 | 2012-01-19Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same
#6 | 2011-06-09System and method for designing integrated circuits that employ adaptive voltage scaling optimization
#7 | 2010-11-18Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
#8 | 2010-06-17Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testing
#9 | 2010-04-15Reducing path delay sensitivity to temperature variation in timing-critical paths
#10 | 2010-04-15Circuit timing analysis incorporating the effects of temperature inversion
#11 | 2009-11-12Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuit
#12 | 2008-02-21Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction
#13 | 2007-11-01Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
#14 | 2007-04-05Method and computer program for detailed routing of an integrated circuit design with multiple routing rules and net constraints
#15 | 2006-12-28Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design
#16 | 2006-07-11Minimal bends connection models for wire density calculation
#17 | 2006-05-25Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism
#18 | 2006-05-09Intelligent crosstalk delay estimator for integrated circuit design flow
#19 | 2006-03-23Method of floorplanning and cell placement for integrated circuit chip architecture with internal I/O ring
#20 | 2006-03-02Method and apparatus for implementing a co-axial wire in a semiconductor chip
#21 | 2006-02-02Method of automated repair of crosstalk violations and timing violations in an integrated circuit design
#22 | 2005-09-20Intelligent engine for protection against injected crosstalk delay
#23 | 2005-06-14Integrated design system and method for reducing and avoiding crosstalk
#24 | 2005-06-14Integrated circuit design system and method for reducing and avoiding crosstalk
#25 | 2005-04-12Wire delay distributed model
#26 | 2005-03-17Method of noise analysis and correction of noise violations for an integrated circuit design
#27 | 2005-03-03Method of clock driven cell placement and clock tree synthesis for integrated circuit design
#28 | 2005-01-27Method of finding critical nets in an integrated circuit design
#29 | 2005-01-11Global chip interconnect
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