US20110309531A1
2011-12-22
13/219,836
2011-08-29
A substrate on which a plurality of epoxy over molded integrated circuit dies are formed includes a beam formed on the substrate for providing stiffness to the substrate. The beam includes structure having a cross-sectional shape, for example, substantially in the shape of a trapezoid, βTβ or βLβ, and may be formed on the top or bottom surface of the substrate.
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Details of semiconductor or other solid state devices; Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Arsenic [As]
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of package parts other than the semiconductor or other solid state devices to be connected Encapsulation
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Technical content checked by a classifier Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Device type Integrated circuits
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Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Wire connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Wire connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
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Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Gold [Au]
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Details of semiconductor or other solid state devices Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups Β -Β , e.g. sealing of a cap to a base of a container Encapsulations, e.g. encapsulation layers, coatings
This application is a divisional of U.S. patent application Ser. No. 12/032,805, filed on Feb. 18, 2008, and entitled MOLDED BEAM FOR OPTOELECTRONIC SENSOR CHIP SUBSTRATE, issuing as U.S. Pat. No. 8,013,456 on Sep. 6, 2011, which application claims benefit of U.S. Provisional Application No. 60/891,238, filed on Feb. 23, 2007, and entitled MOLDED BEAM FOR OPTOELECTRONIC SENSOR, the specifications of which are incorporated by reference herein.
The present invention relates to integrated circuits, and more particularly to integrated circuit fabrication.
Integrated circuits such as, for example, optoelectronic sensors, are typically manufactured as packages in multiple quantities formed from βchipsβ fabricated on printed circuit boards. These packages are constructed by forming integrated circuit dies on a FR4 printed circuit board or Bismaleimide-Thriazine (BT) substrates. The die is wire bonded with, for example, gold wire and then over molded with epoxy to protect the die and the wire bonds. The substrate is then cut into small pieces using a sawing process to form individual integrated circuit packages.
The over mold process utilizes a transfer molded epoxy material. The epoxy material and the substrate on which the integrated circuit dies are formed, have different thermal coefficient of expansions. The combination of the epoxy material and the substrate and the tooling design methods utilized, create large stresses in the individual integrated circuit packages. Stresses in the individual packages are caused by the difference in thermal coefficient of expansion between the mold epoxy and the substrate. The stresses cause the substrate to curl after over molding. As a result of the curling, fixturing is necessary to flatten the substrate prior to the sawing operation.
A need has thus arisen for a substrate and fabrication process which provides additional strength for the substrate to prevent undesired curling of the substrate prior to a sawing operation.
In accordance with the present invention, a substrate on which a plurality of epoxy over molded integrated circuit dies are formed includes a beam formed on the substrate for providing stiffness to the substrate. The beam includes structure having a cross-sectional shape, for example, substantially in the shape of a trapezoid, βTβ or βLβ, and may be formed on the top or bottom surface of the substrate.
For a more complete understanding of the present invention and for further advantages thereof, reference is now made to the following Description of the Preferred Embodiments taken in conjunction with the accompanying Drawings:
FIG. 1 is a pictorial illustration showing a plurality of dies on a substrate;
FIG. 2 is a pictorial illustration showing epoxy over molded dies on a substrate;
FIG. 3 is a pictorial illustration showing use of the present beam molded on the top surface of a substrate;
FIG. 4 is a pictorial illustration showing an individual component severed from a substrate;
FIG. 5 is a pictorial illustration of an alternate embodiment of the present beam;
FIG. 6 is a pictorial illustration of an alternate embodiment of the present beam; and
FIG. 7 is a pictorial illustration of the present beam formed on the bottom surface of a substrate.
Referring to the FIG. 1, a plurality of individual integrated circuit dies 10 are shown fabricated on a substrate 12, having a top surface 12a and a bottom surface 12b (FIG. 7). Substrate 12 may comprise, for example, a FR4 or BT substrate. Dies 10 are wire bonded utilizing wires 14.
FIG. 2 illustrates dies 10 and wires 14 being over molded with epoxy 18 to form integrated circuit packages 16. Epoxy 18 may comprise for example, thermoset epoxy plastic molding compound materials.
Referring now to FIG. 3, an embodiment of the present stiffening beam 22 is illustrated. Beam 22 is formed having a cross-sectional shape substantially in the form of the letter βLβ, and is formed on top surface 12a of substrate 12 adjacent to packages 16. Beam 22 is formed from the same epoxy 18 which over molds dies 10 and wires 14. Beam 22 adds sufficient strength to stabilize substrate 12 thereby preventing substrate 12 from curling prior to the saw operation. Beam 22 is formed in the fabrication process at about the same time as the over molding process of dies 10 takes place.
FIG. 4 illustrates a single package 20 after the sawing operation which severs packages 16 from substrate 12. During the sawing operation, beam 22 is discarded.
FIGS. 5 and 6 illustrate additional embodiments of the present beam. FIG. 5 illustrates a beam 24 having a cross-sectional shape substantially in the form of a trapezoid. FIG. 6 illustrates a beam 25 formed having a cross-sectional shape substantially in the form of the letter βTβ.
FIG. 7 illustrates the use of beam 22 formed on bottom surface 12b of a substrate 12.
Other alterations and modifications of the invention will likewise become apparent to those of ordinary skill in the art upon reading the present disclosure, and it is intended that the scope of the invention disclosed herein be limited only by the broadest interpretation of the appended claims to which the inventors are legally entitled.
1. A substrate comprising:
a substantially planar sheet having a top surface and a bottom surface;
a plurality of epoxy over molded integrated circuit dies formed on the top surface of the sheet, wherein the epoxy over molded integrated circuit dies are separated from each other by a portion of the top surface defining an open area of the sheet between each pair of the epoxy over molded integrated circuit dies; and
an epoxy formed beam molded on the bottom surface of the sheet, wherein the epoxy formed beam is formed only from the epoxy forming the epoxy over molded integrated circuit dies.
2. The substrate of claim 1 wherein the epoxy formed beam has a length and a width, wherein each of the epoxy over molded integrated circuit dies has a length and a width, and wherein the length of the epoxy formed beam is substantially parallel to the length of the epoxy over molded integrated circuit dies.
3. The substrate of claim 1 wherein the epoxy formed beam has a length and a width, wherein each of the epoxy over molded integrated circuit dies has a length and a width, and wherein the length of the epoxy formed beam is substantially identical to the length of the epoxy over molded integrated circuit dies.
4. The substrate of claim 1 wherein the epoxy formed beam has a length and a width, wherein each of the epoxy over molded integrated circuit dies has a length and a width, and wherein the length of the epoxy formed beam is greater than the length of the epoxy over molded integrated circuit dies.
5. A process comprising:
selecting a substantially planar sheet having a top surface and a bottom surface;
forming a plurality of epoxy over molded integrated circuit dies on the top surface of the sheet, wherein the forming separates the epoxy over molded integrated circuit dies from each other by a portion of the top surface defining an open area of the sheet between each pair of the epoxy over molded integrated circuit dies; and
molding an epoxy formed beam on the bottom surface of the sheet, wherein the epoxy formed beam is formed only from the epoxy forming the epoxy over molded integrated circuit dies.
6. The process of claim 5 wherein the epoxy formed beam is not formed simultaneously with the epoxy over molded integrated circuit dies.