212576 ⎘
Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Device type Integrated circuits
Sub-classes:COMPONENT FORMING MACHINE WITH JAMMED COMPONENT MITIGATION
#2METHODS OF FABRICATING 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERS AND MEMORY CELLS
#3METHOD AND APPARATUS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) INTEGRATED THERMOPILE DESIGN
#4HYBRID BONDING WITH UNIFORM PATTERN DENSITY
#5CAPACITIVE COUPLING IN A DIRECT-BONDED INTERFACE FOR MICROELECTRONIC DEVICES
#6THERMAL RESISTOR MANUFACTURING METHOD
#7REDISTRIBUTION LINES HAVING STACKING VIAS
#8ELECTRONIC COMPONENT PACKAGE
#9SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
#10METHODS OF PACKAGING SEMICONDUCTOR DEVICES AND PACKAGED SEMICONDUCTOR DEVICES
#11SEMICONDUCTOR COMPONENTS HAVING CONDUCTIVE VIAS WITH ALIGNED BACK SIDE CONDUCTORS
#123D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE WITH MEMORY CONTROL CIRCUITS
#13PACKAGES WITH METAL LINE CRACK PREVENTION DESIGN
#14PACKAGE WITH TILTED INTERFACE BETWEEN DEVICE DIE AND ENCAPSULATING MATERIAL
#152.5D/3D SYSTEM INTEGRATION
#16SEMICONDUCTOR DEVICE
#17DISPLAY DEVICE HAVING CONNECTION UNIT
#18INTEGRATED CIRCUIT (IC) DEVICE PACKAGING SYSTEM AND METHOD
#19LOW WARPAGE HIGH DENSITY TRENCH CAPACITOR
#20INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME
#21METHOD OF FORMING SEMICONDUCTOR DEVICE USING HIGH STRESS CLEAVE PLANE
#22SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#23PROCESS FOR MANUFACTURING ELECTRONIC COMPONENTS
#24SEMICONDUCTOR STRUCTURE HAVING OPTICAL COMPONENT AND MANUFACTURING METHOD THEREOF
#25INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK
#26Wafer Level Integration of Passive Devices
#27Stacked Semiconductor Device Assembly in Computer System
#28INTEGRATED CIRCUIT STRUCTURE
#29MANUFACTURING METHOD OF PACKAGE DEVICE
#30SEMICONDUCTOR DEVICE
#31SEMICONDUCTOR DEVICE WITH COUPLER STRUCTURE
#323D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLS
#33POWER MODULE AND RELATED METHODS
#34MICROELECTRONIC ASSEMBLY FROM PROCESSED SUBSTRATE
#35PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS
#363D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERS
#37PACKAGE COMPRISING A SUBSTRATE WITH AN INTERCONNECT BLOCK
#38SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
#39SEMICONDUCTOR DEVICE ASSEMBLIES WITH MOLDED SUPPORT SUBSTRATES
#40FIDUCIALS WITH UNDERLYING DUMMY METALLIZATION FOR INTEGRATED CIRCUIT DEVICE ALIGNMENT
#41DOUBLE-SIDED INTEGRATED CIRCUIT WITH STABILIZING CAGE
#423D semiconductor device and structure with metal layers and memory cells
#43SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
#443D SEMICONDUCTOR DEVICE AND STRUCTURE WITH SINGLE-CRYSTAL LAYERS
#45METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYS
#46OPTOELECTRONIC SYSTEM
#47PACKAGED INTEGRATED CIRCUIT DEVICES WITH THROUGH-BODY CONDUCTIVE VIAS, AND METHODS OF MAKING SAME
#48METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES
#49INLINE RESISTOR INTEGRATED WITH CONDUCTIVE CONTACT PAD STRUCTURE
#50THROUGH-HOLE ELECTRODE SUBSTRATE
#51MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING
#523D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY CELLS AND MULTIPLE METAL LAYERS
#53MULTI-DIE MEMORY DEVICE
#54SEMICONDUCTOR DEVICE PACKAGES, PACKAGING METHODS, AND PACKAGED SEMICONDUCTOR DEVICES
#55METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
#56Method for Forming a Semiconductor Device Having TSV Formed Through a Silicon Interposer and a Second Silicon Substrate with Cavity Covering a Second Die
#57AUTONOMOUS ELECTRICAL POWER SOURCES
#583D SEMICONDUCTOR DEVICE AND STRUCTURE WITH METAL LAYERS AND MEMORY CELLS
#59METHOD AND SYSTEM FOR VERIFYING INTEGRATED CIRCUIT STACK
#60INTEGRATED CIRCUITS FOR NEUROTECHNOLOGY AND OTHER APPLICATIONS
#61PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME
#623D semiconductor devices and structures with metal layers
#63Integrated circuit package and method of forming same
#64RIBBON WIRE BOND
#65HYBRID BONDING WITH UNIFORM PATTERN DENSITY
#66THERMAL RESISTOR AND METHOD OF MANUFACTURING THE SAME
#67MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES
#68SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES
#693D SEMICONDUCTOR DEVICES AND STRUCTURES WITH METAL LAYERS
#70SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING FUNCTIONAL AND NON-FUNCTIONAL CONDUCTIVE PADS
#713D semiconductor device and structure with bonding and DRAM memory cells
#72HYBRID BACKSIDE THERMAL STRUCTURES FOR ENHANCED IC PACKAGES
#73STACKED SEMICONDUCTOR DEVICE
#74SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#75Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#763D semiconductor memory device and structure with memory and metal layers
#77SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES
#78Methods and apparatus for measuring analytes using large scale FET arrays
#79INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME
#80SEMICONDUCTOR COMPONENTS HAVING CONDUCTIVE VIAS WITH ALIGNED BACK SIDE CONDUCTORS
#81Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#82SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES
#833D SYSTEM INTEGRATION
#843D semiconductor devices and structures with metal layers
#853D semiconductor device and structure with single-crystal layers
#86Method for forming a semiconductor device including forming a first interconnect structure on one side of a substrate having first metal feature closer the substrate than second metal feature and forming first and second tsv on other side of substrate connecting to the metal features
#87SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE
#88Stacked semiconductor device assembly in computer system
#89PACKAGES WITH METAL LINE CRACK PREVENTION DESIGN
#90Display device having connection unit
#91Solder material
#92Semiconductor package and method of fabricating semiconductor package
#93MULTILAYER ELECTRICAL CONDUCTORS FOR TRANSFER PRINTING
#94SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER
#953D semiconductor device and structure with bonding
#96Method And Apparatus For Fault Isolation, Computer Device, Medium And Program Product
#97MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER
#98Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#99Memory System Topologies Including A Memory Die Stack
#100Semiconductor device packages, packaging methods, and packaged semiconductor devices
#101MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME
#102Package structure and method of forming the same
#1033D semiconductor device and structure with bonding
#104Semiconductor package and method of fabricating semiconductor package
#105FLIP CHIP SELF-ALIGNMENT FEATURES FOR SUBSTRATE AND LEADFRAME APPLICATIONS
#106Semiconductor Device and Method of Manufacture
#107Low warpage high density trench capacitor
#108Multi-die memory device
#1093D semiconductor device and structure with single-crystal layers
#1102.5D/3D ELECTRONIC PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME
#111Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#112INVERTED LEADS FOR PACKAGED ISOLATION DEVICES
#113Method of forming semiconductor device using high stress cleave plane
#114Light engine based on silicon photonics TSV interposer
#115SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
#116Shielded electronic component package
#117Method and system for verifying integrated circuit stack having photonic device
#118SEMICONDUCTOR DEVICE PACKAGES INCLUDING AN INDUCTOR AND A CAPACITOR
#119Integrated circuit assembly with hybrid bonding
#120Three-dimensional functional integration
#121Structurally embedded and inhospitable environment systems having autonomous electrical power sources
#122PROTECTION OF INTEGRATED CIRCUITS
#123Power module and related methods
#124SEMICONDUCTOR DEVICE
#1253D INTEGRATED CIRCUIT (3DIC) STRUCTURE
#126Integrated circuit device having redistribution pattern
#127Autonomous electrical power sources
#128Systems and methods to monitor leakage current
#129Semiconductor device and method for manufacturing the same
#130Packaged integrated circuit devices with through-body conductive vias, and methods of making same
#131Semiconductor device and a method of manufacturing the same
#132Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
#133METHOD FOR MANUFACTURING COMPOSITE LAYER CIRCUIT STRUCTURE OF ELECTRONIC DEVICE
#134Semiconductor device
#1353D semiconductor device and structure with bonding
#136Single-package wireless communication device
#137Semiconductor device and method of manufacturing the same
#138ELECTRONIC COMPONENT PACKAGE
#139Illumination apparatus
#1403D semiconductor device and structure with single-crystal layers
#141Package-on-package (PoP) semiconductor package and electronic system including the same
#142MICRO DEVICE TRANSFER HEAD ASSEMBLY
#143Semiconductor device
#144Ball grid array current meter with a current sense wire
#145Semiconductor device
#146ELECTROMAGNETIC SHIELDS WITH BONDING WIRES FOR SUB-MODULES
#147Thermal resistor and method of manufacturing the same
#148Methods and apparatus for measuring analytes using large scale FET arrays
#1493D HETEROGENEOUS INTEGRATIONS AND METHODS OF MAKING THEREOF
#150Capacitive coupling in a direct-bonded interface for microelectronic devices
#151Semiconductor chip with redundant thru-silicon-vias
#152Package device
#153ENHANCED SEMICONDUCTOR STRUCTURES
#154Multilayer electrical conductors for transfer printing
#155Integrated circuit package having wirebonded multi-die stack
#156Impedance controlled electrical interconnection employing meta-materials
#1573D semiconductor memory device and structure
#158Build-up package for integrated circuit devices, and methods of making same
#159Hybrid nanosilver/liquid metal ink composition and uses thereof
#160Multi-chip semiconductor package
#161Semiconductor package device and method of manufacturing the same
#162MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER
#1633D semiconductor device and structure with memory
#164Chip package structure with integrated device integrated beneath the semiconductor chip
#165Semiconductor device and method of manufacture
#166Semiconductor device with contact pad and method of making
#167System and method for physically detecting counterfeit electronics
#168Semiconductor device with sealed semiconductor chip
#169Source/drain regions in integrated circuit structures
#170Semiconductor device having electrode pads arranged between groups of external electrodes
#171IC having a metal ring thereon for stress reduction
#172MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING
#1733D semiconductor device and structure with single-crystal layers
#174Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
#175EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME
#176Memory system topologies including a memory die stack
#177Burn-in board and burn-in apparatus
#1783D semiconductor devices and structures with metal layers
#179Wafer Level Integration of Passive Devices
#180Light engine based on silicon photonics TSV interposer
#181Stacked semiconductor device assembly in computer system
#182Secure semiconductor integration and method for making thereof
#183Packaged integrated circuit devices with through-body conductive vias, and methods of making same
#184Semiconductor device with a semiconductor chip connected in a flip chip manner
#185Microelectronic assembly from processed substrate
#186Microelectronic assemblies having conductive structures with different thicknesses on a core substrate
#187Bonded semiconductor structures
#188Resonant-coupled transmission line
#1893D semiconductor memory device and structure
#190Pad structure for front side illuminated image sensor
#191Reduction in susceptibility of analog integrated circuits and sensors to radio frequency interference
#192Through-hole electrode substrate
#193Package with Tilted Interface Between Device Die and Encapsulating Material
#194Display device having connection unit
#195Semiconductor device and measurement device
#196Integrated circuit structure
#197Power module and related methods
#198Semiconductor device packages, packaging methods, and packaged semiconductor devices
#199Electro-optical package and method of fabrication
#200Hybrid bonding with uniform pattern density
#201EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME
#202Method for permanent connection of two metal surfaces
#2033D INTEGRATED CIRCUIT (3DIC) STRUCTURE
#204Semiconductor memory device structure
#205PLANAR INTEGRATED CIRCUIT PACKAGE INTERCONNECTS
#206Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices
#207Method of forming integrated circuit package
#208Interconnect structure with redundant electrical connectors and associated systems and methods
#209Memories and memory components with interconnected and redundant data interfaces
#210Multi-die memory device
#211Stacked semiconductor device
#212PACKAGED MICROELECTRONIC DEVICES HAVING STACKED INTERCONNECT ELEMENTS AND METHODS FOR MANUFACTURING THE SAME
#2133D semiconductor devices and structures with at least two single-crystal layers
#214Scalable high-bandwidth connectivity
#215Integrated circuit assembly with hybrid bonding
#2163D semiconductor memory device and structure
#2173D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
#218ANISOTROPIC CONDUCTIVE FILM AND PRODUCTION METHOD OF THE SAME
#2193D semiconductor device and structure with high-k metal gate transistors
#220Electronic device having inverted lead pins
#221DESIGNS AND METHODS FOR CONDUCTIVE BUMPS
#222Shielded electronic component package
#223Semiconductor device package comprising power module and passive elements
#224Semiconductor device
#225SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP
#226Die stack with cascade and vertical connections
#227Multichip package manufacturing process
#228Illumination apparatus
#229PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES
#230Shielded fan-out packaged semiconductor device and method of manufacturing
#231Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
#232Protection of integrated circuits
#233Circuit board structure and method for manufacturing a circuit board structure
#234Packages and methods of forming packages
#235Pattern decomposition lithography techniques
#236Post passivation interconnect
#237Methods of manufacturing an integrated circuit having stress tuning layer
#238Repurposed seed layer for high frequency noise control and electrostatic discharge connection
#239Manufacturing method of semiconductor device and semiconductor device
#240Memory system topologies including a memory die stack
#241Protection of wire-bond ball grid array packaged integrated circuit chips
#242Multilayer electrical conductors for transfer printing
#243Methods and devices for fabricating and assembling printable semiconductor elements
#244System on integrated chips and methods of forming same
#245Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
#246Method for producing a 3D semiconductor memory device and structure
#247Packages with metal line crack prevention design
#248Amplifier module
#249Integrated circuit package and method of forming same
#2503D IC method and device
#251Source/drain regions in integrated circuit structures
#252Methods for producing a 3D semiconductor memory device and structure
#253Semiconductor device package comprising power module and passive elements
#254Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
#255Inorganic dies with organic interconnect layers and related structures
#256Semiconductor device and a method of manufacturing the same
#257Methods for attachment and devices produced using the methods
#258Silicon interposer sandwich structure for ESD, EMC, and EMC shielding and protection
#259Method of manufacturing an augmented LED array assembly
#2603D IC method and device
#261Redistribution Lines Having Stacking Vias
#262Semiconductor device
#263Crack sensor for sensing cracks in a solder pad, and method for production quality control
#264SEMICONDCTOR DEVICE PACKAGE THERMAL CONDUIT
#265Ribbon wire bond
#266Semiconductor device
#267Flip chip curved sidewall self-alignment features for substrate and method for manufacturing the self-alignment features
#268IC package having a metal die for ESP protection
#269Integrated circuit package with a magnetic core
#270Methods for producing a 3D semiconductor memory device and structure
#271Hybrid backside thermal structures for enhanced IC packages
#272Semiconductor package and manufacturing method thereof
#273Package-on-package (PoP) semiconductor package and electronic system including the same
#274Semiconductor structure and method for making thereof
#275Method of forming semiconductor device using range compensating material
#276Resist structure for forming bumps
#277Semiconductor device with frame having arms
#2783D semiconductor device and structure with multiple isolation layers
#279Semiconductor device and semiconductor module
#280THERMOCOMPRESSION BONDING WITH PASSIVATED SILVER-BASED CONTACTING METAL
#281Thermocompression Bonding with Passivated Gold Contacting Metal
#282Thermocompression bonding with passivated copper-based contacting metal
#283Thermocompression Bonding with Passivated Tin-Based Contacting Metal
#284Semiconductor device assemblies with molded support substrates
#285Thermocompression bonding with passivated nickel-based contacting metal
#286Thermocompression bonding using metastable gas atoms
#287Structure for bonding and electrical contact for direct bond hybridization
#288Metal surface preparation for increased alignment contrast
#289Interconnect structure with redundant electrical connectors and associated systems and methods
#290Alignment features for hybridized image sensor
#291METHODS AND APPARATUS FOR WAFER-LEVEL PACKAGING USING DIRECT WRITING
#292Stacked semiconductor device and test method thereof
#293INORGANIC DIES WITH ORGANIC INTERCONNECT LAYERS AND RELATED STRUCTURES
#294Inorganic dies with organic interconnect layers and related structures
#2953D SEMICONDUCTOR DEVICE AND STRUCTURE
#296Multi-die memory device
#297Integrated circuits for neurotechnology and other applications
#298Back side metallization
#299Ultra-thin multichip power devices
#300Package structures and method of forming the same