Austin, Texas
United States
33
2026-04-30
The entities that hold a legal rights for patent applications filed by inventor O'Connor James Michael:
James Michael O'Connor from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
GATHER ACCELERATED ADDRESS SPACE
#2 | 2025-01-30TECHNIQUES FOR PERFORMING MATRIX COMPUTATIONS USING HIERARCHICAL REPRESENTATIONS OF SPARSE MATRICES
#3 | 2024-12-12PROCESSOR AND MEMORY COMMUNICATION IN A STACKED MEMORY SYSTEM
#4 | 2024-08-22COMPUTATION OFFLOAD REQUESTS WITH DENIAL RESPONSE
#5 | 2024-08-01Memory page access instrumentation
#6 | 2024-06-27Hierarchical network for stacked memory system
#7 | 2023-12-07Combined on-package and off-package memory system
#8 | 2023-10-05Application partitioning for locality in a stacked memory system
#9 | 2023-09-21LOCATING A MEMORY UNIT ASSOCIATED WITH A MEMORY ADDRESS UTILIZING A MAPPER
#10 | 2023-09-21Hierarchical network for stacked memory system
#11 | 2023-08-31MEMORY STACKED ON PROCESSOR FOR HIGH BANDWIDTH
#12 | 2023-03-09Prefetch kernels on data-parallel processors
#13 | 2023-02-09MEMORY INTERFACE WITH REDUCED ENERGY TRANSMIT MODE
#14 | 2022-11-24Techniques for performing matrix computations using hierarchical representations of sparse matrices
#15 | 2022-11-24Techniques for accelerating matrix multiplication computations using hierarchical representations of sparse matrices
#16 | 2022-11-24Techniques for generating and processing hierarchical representations of sparse matrices
#17 | 2022-10-27Combined on-package and off-package memory system
#18 | 2020-07-30Reducing coupling and power noise on PAM-4 I/O interface
#19 | 2020-07-02Prefetch kernels on data-parallel processors
#20 | 2019-10-03Unrelaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses
#21 | 2019-10-03Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O
#22 | 2019-10-03424 encoding schemes to reduce coupling and power noise on PAM-4 data buses
#23 | 2019-10-03Relaxed 433 encoding to reduce coupling and power noise on PAM-4 data buses
#24 | 2017-09-07Systems and methods for dynamic random access memory (DRAM) sub-channels
#25 | 2016-02-25System and method for page-conscious GPU instruction
#26 | 2014-12-25Method and system for asymmetrical processing with managed data affinity
#27 | 2014-05-29Prefetch kernels on a graphics processing unit
#28 | 2013-06-20Interconnect Redundancy for Multi-Interconnect Device
#29 | 2013-06-20Data bus inversion coding
#30 | 2012-12-11Zero-bandwidth clears
#31 | 2011-12-22Bandwidth adaptive memory compression
#32 | 2011-11-03System and method for low-latency data compression/decompression
#33 | 2011-01-11Write buffer for read-write interlocks
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