Ilyas Mohammed

Compressive sensing based image processing

3D CHIP SHARING DATA BUS

Packaged Cold Plate Lids For Optimized Cooling Of High Power Chip Packages And Systems And Methods Incorporating Same

3D CHIP WITH SHARED CLOCK DISTRIBUTION NETWORK

Optical Packages with LED Interconnects

High Speed Optical Links for High-Bandwidth Memory Systems

Advanced Substrates for Large, High Performance Power Packages

Capacitor Carrier Ring And Stiffener For Integrated Circuit Package Assembly

Systems For High-Speed Computing Using An Optical Interchange

3D chip sharing data bus

3D chip with shared clock distribution network

Direct-bonded lamination for improved image clarity in optical devices

Compressive sensing based image processing

3D chip sharing data bus

3D chip with shared clock distribution network

Training network for compressive sensing based image processing

Compressive sensing based image capture using dynamic masking

Compressive sensing based image capture using multi-lens array

Over and under interconnects

3D chip with shared clock distribution network

Stacked IC structure with system level wiring on multiple sides of the IC die

3D processor having stacked integrated circuit die

3D chip sharing power interconnect layer

Face-to-face mounted IC dies with orthogonal top interconnect layers

3D processor

3D compute circuit with high density Z-axis interconnects

3D Compute circuit with high density z-axis interconnects

3D chip sharing clock interconnect layer

3D chip with shielded clock lines

3D chip sharing data bus circuit

Face-to-face mounted IC dies with orthogonal top interconnect layers

3D chip sharing data bus

Stacked IC structure with system level wiring on multiple sides of the IC die

3D chip sharing power circuit

3D chip sharing power interconnect layer

Method of manufacturing embedded packaging with preformed vias

Semiconductor chip assembly and method for making same

Microelectronic package with consolidated chip structures

Microelectronic packages having cavities for receiving microelectronic elements

Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface

Stacked microelectronic assembly with TSVs formed in stages with plural active chips

Low-stress vias

HYBRID INTERPOSER

Memory module in a package

Memory module in a package

Package-on-package assembly with wire bonds to encapsulation surface

Stacking packages with alignment elements

Enabling uniformity of stacking process through bumpers