Patents-Review.com
ClassID:

189506 ⎘

G06F7/49968 - CPC Classification

Classification description:

Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Denomination or exception handling, e.g. rounding or overflow; Significance control; Rounding Rounding towards positive infinity

Recent Application in this class:
#1
20230342112
2023-10-26

Decimal floating-point instruction in a round-for-reround mode

 #2
20230214179
2023-07-06

FLOATING POINT FUSED MULTIPLY ADD WITH MERGED 2'S COMPLEMENT AND ROUNDING

 #3
20210385094
2021-12-09

Physical unclonable function based true random number generator, method for generating true random numbers, and associated electronic device

 #4
20210382688
2021-12-09

Modular operation circuit adopting iterative calculations

 #5
20210004206
2021-01-07

Prepare for shorter precision (round for reround) mode in a decimal floating-point instruction

 #6
20200233642
2020-07-23

Enhanced low precision binary floating-point formatting

 #7
20190377550
2019-12-12

Round for reround mode in a decimal floating point instruction

 #8
20190369960
2019-12-05

Enhanced low precision binary floating-point formatting

 #9
20190079730
2019-03-14

Round for reround mode in a decimal floating point instruction

 #10
20180373500
2018-12-27

Compiler controls for program language constructs

 #11
20180373499
2018-12-27

Compiler controls for program language constructs

 #12
20180121165
2018-05-03

Round for reround mode in a decimal floating point instruction

 #13
20170199724
2017-07-13

Round for reround mode in a decimal floating point instruction

 #14
20160306608
2016-10-20

Accumulation of floating-point values

 #15
20160070538
2016-03-10

Round for reround mode in a decimal floating point instruction

 #16
20140181169
2014-06-26

Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags

 #17
20130226981
2013-08-29

Round for reround mode in a decimal floating point instruction

 #18
20090024684
2009-01-22

Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

 #19
20080215659
2008-09-04

Round for reround mode in a decimal floating point instruction

 #20
20060101107
2006-05-11

Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units

 #21
20060064454
2006-03-23

Processing unit having decimal floating-point divider using Newton-Raphson iteration