207304 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups - , e.g. sealing of a cap to a base of a container; Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
FLIP-CHIP BONDING STRUCTURE AND CIRCUIT BOARD THEREOF
#2FLIP-CHIP STACKING STRUCTURES AND METHODS FOR FORMING THE SAME
#3FLIP-CHIP STACKING STRUCTURES AND METHODS FOR FORMING THE SAME
#4Semiconductor Package and Method
#5SEMICONDUCTOR STRUCTURE WITH PULL-IN PLANARIZATION LAYER AND METHOD FORMING THE SAME
#6SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME
#7SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#8Semiconductor Package and Method
#9ELECTRONIC DEVICES INCLUDING VENT OPENINGS AND ASSOCIATED METHODS
#10MICROELECTRONICS DEVICE PACKAGE AND METHODS
#11FLIP-CHIP BONDING STRUCTURE AND CIRCUIT BOARD THEREOF
#12SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
#13MANUFUCTURING METHOD OF PACKAGING STRUCTURE FOR BIPOLAR TRANSISTOR WITH CONSTRICTED BUMPS
#14SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#15METHODS AND APPARATUS TO REDUCE DEFECTS IN INTERCONNECTS BETWEEN SEMICONDCUTOR DIES AND PACKAGE SUBSTRATES
#16METHODS AND APPARATUS TO REDUCE DEFECTS IN INTERCONNECTS BETWEEN SEMICONDCUTOR DIES AND PACKAGE SUBSTRATES
#17MULTILEVEL PACKAGE SUBSTRATE DEVICE WITH BGA PIN OUT AND COAXIAL SIGNAL CONNECTIONS
#18Scalable Extreme Large Size Substrate Integration
#19Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
#20MULTI-LEVEL DIE COUPLED WITH A SUBSTRATE
#21Semiconductor package and method for making the same
#22Semiconductor Structure with Pull-in Planarization Layer and Method Forming the Same
#23Flip-chip stacking structures and methods for forming the same
#24SEMICONDUCTOR PACKAGE AND METHOD
#25Semiconductor device and manufacturing method thereof
#26SEMICONDUCTOR MODULE MANUFACTURING METHOD, ELECTRONIC EQUIPMENT MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND ELECTRONIC EQUIPMENT
#27Semiconductor device assembly with embossed solder mask having non-planar features and associated methods and systems
#28SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
#29PIN-GRID-ARRAY-TYPE SEMICONDUCTOR PACKAGE
#30Passivation layer and planarization layer and method of forming the same
#31Cap for package of integrated circuit
#32Packaging structure for bipolar transistor with constricted bumps
#33Scalable extreme large size substrate integration
#34Semiconductor package and method for making the same
#35Multi-level components for integrated-circuit packages
#36Passive devices in package-on-package structures and methods for forming the same
#37Method for manufacturing semiconductor device
#38Through-package partial via on package edge
#39Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
#40System and method for forming solder bumps
#41Semiconductor device comprising semiconductor die and interposer and manufacturing method thereof
#42Sintered Metal Flip Chip Joints
#43SEMICONDUCTOR PACKAGE WITH AN INTERNAL HEAT SINK AND METHOD FOR MANUFACTURING THE SAME
#44Semiconductor device and manufacturing method thereof
#45Co-packaged die on leadframe with common contact
#46SEMICONDUCTOR DEVICE WITH AN ELECTROMAGNETIC INTERFERENCE (EMI) SHIELD
#47Cap for package of integrated circuit
#48Method of bonding terminal of semiconductor chip using solder bump and semiconductor package using the same
#49METHOD FOR PRINTING MICRO LINE PATTERN USING INKJET TECHNOLOGY
#50Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
#51ELECTRONIC DEVICE PACKAGE
#52Mechanically anchored C4 pad and method of forming same
#53Method of fabricating an integrated fan-out package
#54Passive devices in package-on-package structures and methods for forming the same
#55Semiconductor device and manufacturing method thereof
#56Semiconductor device and manufacturing method thereof
#57Integrated fan-out package and method of fabricating the same
#58Method for manufacturing wafer-level semiconductor packages
#59Chip package structure and manufacturing method thereof
#60Integrated fan-out package and method of fabricating the same
#61Packaged semiconductor device and method of fabricating a packaged semiconductor device
#62Sintered Metal Flip Chip Joints
#63Underfill dispensing using funnels
#64Electronic device package
#65Chip package and method for forming the same
#66Underfill dispensing using funnels
#67LEAD-FREE SOLDER BUMP JOINING STRUCTURE
#68Electronic package, semiconductor substrate of the electronic package, and method for manufacturing the electronic package
#69SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#70A SEMICONDUCTOR PACKAGE HAVING AN ETCHED GROOVE FOR AN EMBEDDED DEVICE FORMED ON BOTTOM SURFACE OF A SUPPORT SUBSTRATE AND A METHOD FOR FABRICATING THE SAME
#71Semiconductor device having an encapsulated front side and interposer and manufacturing method thereof
#72Electronic device
#73SEMICONDUCTOR DEVICE WITH AN ELECTROMAGNETIC INTERFERENCE (EMI) SHIELD
#74Semiconductor package and method of manufacturing the same
#75Method for producing a power semiconductor module
#76Terminations
#77Semiconductor device and method for manufacturing the same
#78IC structure with angled interconnect elements
#79Semiconductor device and manufacturing method thereof
#80Bump-on-trace structures with high assembly yield
#81CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
#82Semiconductor device and manufacturing method thereof
#83Semiconductor package and manufacturing method thereof
#84Co-packaged die on leadframe with common contact
#85Wiring substrate and method of manufacturing the same
#86Method for insulating singulated electronic die
#87Flip chip package and manufacturing method thereof
#88Method for forming a passive device on a package-on-package structure
#89Semiconductor device and manufacturing method thereof
#90Chip package and method for forming the same
#91Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
#92Laser subassembly metallization for heat assisted magnetic recording
#93Bump-on-trace structures with high assembly yield
#94Thin plastic leadless package with exposed metal die paddle
#95Chip package and method for forming the same
#96Bump-on-trace structures with high assembly yield
#97Apparatus and method of attaching solder ball and method of fabricating semiconductor package including solder ball
#98Ablation method and recipe for wafer level underfill material patterning and removal
#99Passive devices in package-on-package structures and methods for forming the same
#100Method for manufacturing light emitting diode chip
#101Laser subassembly metallization for heat assisted magnetic recording
#102Light emitting diode and method for manufacturing the same
#103Semiconductor device and method of manufacturing the same
#104Thin plastic leadless package with exposed metal die paddle
#105MICROELECTRONIC DIE INCLUDING SOLDER CAPS ON BUMPING SITES THEREOF AND METHOD OF MAKING SAME
#106System and method for forming solder bumps
#107High heat dissipation stacked chip package structure and the manufacture method thereof
#108Radio frequency device packages and methods of formation thereof