SOI structure for signal isolation and linearity

Method of making a semiconductor layer having at least two different thicknesses

METHOD FOR FORMING COMPONENTS ON A SILICON-GERMANIUM LAYER

Method for improving anti-radiation performance of SOI structure

Thermally oxidized heterogeneous composite substrate and method for manufacturing same

Method for coupling a graphene layer and a substrate and device comprising the graphene/substrate structure obtained

Vapor-trapping growth of single-crystalline graphene flowers

Methods of fabricating silicon-on-insulator (SOI) semiconductor devices using blanket fusion bonding

RF switch on high resistive substrate

Isolation structure

Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods

Semiconductor device including dummy isolation gate structure and method of fabricating thereof

Methods of fabricating bipolar junction transistors with reduced epitaxial base facets effect for low parasitic collector-base capacitance

Method of manufacturing semiconductor device

Method of fabricating isolated capacitors and structure thereof

Fabrication method of semiconductor apparatus

Semiconductor device and method for manufacturing the same

Extremely thin semiconductor-on-insulator with back gate contact

Extremely thin semiconductor-on-insulator with back gate contact

Silicon on nothing devices and methods of formation thereof

Methods of forming 3-D semiconductor devices using a replacement gate technique and a novel 3-D device

Method of fabricating isolated capacitors and structure thereof

Method for manufacturing a composite wafer having a graphite core

Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type

Method for measuring film thickness of SOI layer of SOI wafer

Semiconductor body with a buried material layer and method

Radiation hardened SOI structure and method of making same

Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators

Passive devices for FinFET integrated circuit technologies

Optical input/output device for photo-electric integrated circuit device and method of fabricating same

Process for fabricating a silicon-on-insulator structure

SOI structure and method for utilizing trenches for signal isolation and linearity

Selective amorphization for electrical signal isolation and linearity in SOI structures

SOI STRUCTURES WITH REDUCED METAL CONTENT

Controlled process and resulting device

Semiconductor structure and method for manufacturing the same

INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE

STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PROCESS

Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic suppressing region

Method for forming SOI substrate and apparatus for forming the same

Method and apparatus for electroplating on SOI and bulk semiconductor wafers

METHOD FOR DESIGNING SOI WAFER AND METHOD FOR MANUFACTURING SOI WAFER

Method of fabricating isolated capacitors and structure thereof

SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER

Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods

PRECISE OXIDE DISSOLUTION

Semiconductor device and method for manufacturing the same

Semiconductor structure and circuit including ordered arrangement of graphene nanoribbons, and methods of forming same

INSULATING REGION FOR A SEMICONDUCTOR SUBSTRATE

Substrate for integrated circuit and method for forming the same

IIIOxNy ON REO/Si

Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core

Method for manufacturing nitride semiconductor crystal layer

Semiconductor device manufacturing method

Method of fabricating isolated capacitors and structure thereof

Monolithic Nuclear Event Detector and Method of Manufacture

CONTROLLED PROCESS AND RESULTING DEVICE

PROCESS TO DISSOLVE THE OXIDE LAYER IN THE PERIPHERAL RING OF A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE

Thin-BOX metal backgate extremely thin SOI device

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

Optical input/output device for photo-electric integrated circuit device and method of fabricating same

Methods for processing silicon on insulator wafers

SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER AND METHOD

Systems and methods for reducing contact to gate shorts

Semiconductor devices and methods of forming the same

Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

Method for making complementary P and N MOSFET transistors, electronic device including such transistors, and processor including at least one such device

Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness

Semiconductor on insulator

Semiconductor device and method for manufacturing the same

Shared gate for conventional planar device and horizontal CNT

Oxidation after oxide dissolution

Controlled process and resulting device

STRAINED-SILICON CMOS DEVICE AND METHOD

SOI wafers having MOoxide layers on a substrate wafer and an amorphous interlayer adjacent the substrate wafer

LOW COST SOI SUBSTRATES FOR MONOLITHIC SOLAR CELLS

Semiconductor device manufacturing method

Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region

PRECISE OXIDE DISSOLUTION

Bottom electrode for memory device and method of forming the same

SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES

Method for forming silicon oxide film of SOI wafer

Semiconductor component with stress-absorbing semiconductor layer

HEAT REMOVAL FACILITATED WITH DIAMOND-LIKE CARBON LAYER IN SOI STRUCTURES

Structured strained substrate for forming strained transistors with reduced thickness of active layer

SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

TRANSIENT LIQUID PHASE EUTECTIC BONDING

Process for producing localised GeOI structures, obtained by germanium condensation

Integrated circuit structure having bottle-shaped isolation

Semiconductor on insulator apparatus

Method for preparing a germanium layer from a silicon-germanium-on-isolator substrate

STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS

Germanium on insulator (GOI) semiconductor substrates

STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS

Systems and methods for reducing contact to gate shorts

STRAINED-SILICON CMOS DEVICE AND METHOD

Ultra thin silicon on insulator

Butted source contact and well strap

Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations

Method for fabricating an ultra thin silicon on insulator

Semiconductor device and method for manufacturing the same

METHOD OF TRIMMING A HARD MASK LAYER, METHOD FOR FABRICATING A GATE IN A MOS TRANSISTOR, AND A STACK FOR FABRICATING A GATE IN A MOS TRANSISTOR

Method for reducing an unevenness of a surface and method for making a semiconductor device

Hybrid Wafers

Manufacturing method for a semi-conductor on insulator substrate comprising a localised Ge enriched step

Semiconductor integrated circuit device

Method and apparatus for electroplating on soi and bulk semiconductor wafers

Method and device for controlled cleaving process

Semiconductor structure

Laser annealing method and semiconductor device fabricating method

Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

Semiconductor memory device manufacturing method and semiconductor memory device

Semiconductor on insulator apparatus

Method for reducing overlap capacitance in field effect transistors

Controlled process and resulting device

Defect reduction by oxidation of silicon

Semiconductor wafer and process for its production

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Selective incorporation of charge for transistor channels

Bottom electrode for memory device and method of forming the same

Method for manufacturing semiconductor device

Controlled cleaving process

Method of forming high voltage semiconductor device and the high voltage semiconductor device using the same

Integrated assist features for epitaxial growth

LDMOS device and method

Method for reducing overlap capacitance in field effect transistors

Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor

METHOD FOR FORMING FULLY SILICIDED GATES

Systems and methods for reducing contact to gate shorts

Semiconductor Device and Method of Manufacturing a Semiconductor Device

Memory device having implanted oxide to block electron drift, and method of manufacturing the same

Relaxed low-defect SGOI for strained SI CMOS applications

Method of manufacturing semiconductor device

High-quality SGOI by annealing near the alloy melting point

Method for manufacturing semiconductor device and semiconductor device

Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels

DISPOSABLE SEMICONDUCTOR DEVICE SPACER WITH HIGH SELECTIVITY TO OXIDE

Method and device for controlled cleaving process

Semiconductor structure with enhanced performance using a simplified dual stress liner configuration

Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby

Semiconductor device and method of fabricating the same

New Structure for Microelectronics and Microsystem and Manufacturing Process

MOS transistor and fabrication thereof

Method for forming a strained transistor by stress memorization based on a stressed implantation mask

Semiconductor devices having selectively tensile stressed gate electrodes and methods of fabricating the same

Semiconductor devices having torsional stresses

SILICON ON INSULATOR STRUCTURE WITH A SINGLE CRYSTAL CZ SILICON DEVICE LAYER HAVING A REGION WHICH IS FREE OF AGGLOMERATED INTRINSIC POINT DEFECTS

Method of selective formation of compound semiconductor-on-silicon wafer with silicon nanowire buffer layer

Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment

CMOS devices with stressed channel regions, and methods for fabricating the same

Method for producing SiGebased zones with different contents in Ge on a same substrate by condensation of germanium

METHOD OF INCREASING TRANSISTOR PERFORMANCE BY DOPANT ACTIVATION AFTER SILICIDATION

Semiconductor on insulator structure made using radiation annealing

Compound semiconductor-on-silicon wafer with a thermally soft insulator

Single-crystal layer on a dielectric layer

Method for providing mixed stacked structures, with various insulating zones and/or electrically conducting zones vertically localized

SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES AND SEMICONDUCTOR DEVICES USING VOID SPACES

Method for reducing overlap capacitance in field effect transistors

Laser annealing method and semiconductor device fabricating method

STRESS ENGINEERING FOR CAP LAYER INDUCED STRESS

Butted source contact and well strap

Single-crystal layer on a dielectric layer

Method for producing a substrate by germanium condensation

Microstructure for formation of a silicon and germanium on insulator substrate of Si1-XGeX type

SOI substrate, mask blank for charged particle beam exposure, and mask for charged particle beam exposure

Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels

Method for manufacturing semiconductor substrate

Selective incorporation of charge for transistor channels

Structure for reducing overlap capacitance in field effect transistors

Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer

Method for forming semiconductor wafer having insulator

Method of manufacture for a component including at least one single-crystal layer on a substrate

SRAM cell with improved layout designs

Controlled process and resulting device

Controlled process and resulting device

Semiconductor component arrangement having a first and second region

SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Strained-silicon CMOS device and method

Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer

Method for fabricating high tensile stress film and strained-silicon transistors

Integration scheme method and structure for transistors using strained silicon

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Bottom electrode for memory device and method of forming the same

Method and structure for shallow trench isolation during integrated circuit device manufacture

Structure for reducing overlap capacitance in field effect transistors

Formation of strained Si channel and SiGesource/drain structures using laser annealing

Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device

Shared gate for conventional planar device and horizontal CNT

Process for forming an electronic device including discontinuous storage elements

Process for forming an electronic device including discontinuous storage elements

Method for manufacturing a semiconductor substrate and method for manufacturing a semiconductor device

Method of manufacturing a non-volatile semiconductor device

Element fabrication substrate

Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer

Semiconductor integrated circuit device

Structure and method for making strained channel field effect transistor using sacrificial spacer

Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

Recessed gate structures including blocking members, methods of forming the same, semiconductor devices having the recessed gate structures and methods of forming the semiconductor devices

Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer

Super anneal for process induced strain modulation

Semiconductor integrated circuit device and design method thereof

Semiconductor device and method for manufacturing the same

Semiconductor memory device

Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers

STI formation in semiconductor device including SOI and bulk silicon regions

Field effect transistor with mixed-crystal-orientation channel and source/drain regions

GeSOI transistor with low junction current and low junction capacitance and method for making the same

Growth method for nitride semiconductor epitaxial layers

Smooth surface liquid phase epitaxial germanium

High-density germanium-on-insulator photodiode array

Controlled cleaving process

Method of making empty space in silicon

Production method for semiconductor component with stress-carrying semiconductor layer

Method with mechanically strained silicon for enhancing speed of integrated circuits or devices

Technique for creating different mechanical strain in different channel regions by forming an etch stop layer stack having differently modified intrinsic stress

Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor

Structure and method for making strained channel field effect transistor using sacrificial spacer

Silicon-insulator-silicon structure and method for fabricating the same

Use of thin SOI to inhibit relaxation of SiGe layers

Method of making cavities in a semiconductor wafer

Relaxed, low-defect SGOI for strained Si CMOS applications

Strain enhanced ultra shallow junction formation

Methods of fabricating strained-channel FET having a dopant supply region

Technique for transferring strain into a semiconductor region

Silicon-on insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same

Semiconductor device and manufacturing method thereof

Structures and methods for manufacturing p-type MOSFET with graded embedded silicon-germanium source-drain and/or extension

STI formation in semiconductor device including SOI and bulk silicon regions

Semiconductor device and method for producing the same

Non-volatile semiconductor memory device and method for producing same

Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby

High-quality SGOI by oxidation near the alloy melting temperature

Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same

SOI substrate and method of manufacturing the same

Controlled cleaving process

MOSFET performance improvement using deformation in SOI structure

Manufacturing device for buried insulating layer type single crystal silicon carbide substrate

Process for implementing oxygen into a silicon wafer having a region which is free of agglomerated intrinsic point defects

Methods of fabricating semiconductor-on-insulator (SOI) substrates and semiconductor devices using sacrificial layers and void spaces

Semiconductor device and method for manufacturing the same

Element fabrication substrate

MOSFET performance improvement using deformation in SOI structure

Versatile system for limiting mobile charge ingress in SOI semiconductor structures

Use of thin SOI to inhibit relaxation of SiGe layers

Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of SiGelayer

Method of manufacturing semiconductor device having thin film SOI structure

Defect reduction by oxidation of silicon

Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers

Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit

Device structures with multiple nitrided layers

Method of manufacturing a semiconductor wafer having an SOI configuration

Passivated germanium-on-insulator lateral bipolar transistors

MOS transistor and method of manufacturing the same

Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity

Efficient buried oxide layer interconnect scheme

Method for fabricating semiconductor device