Inverter, logic circuit including an inverter and methods of fabricating the same

Display device and manufacturing method thereof

Nonvolatile memory device and method of fabricating the same

Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines

Deep trench (DT) metal-insulator-metal (MIM) capacitor

Three-dimensional memory devices and methods of manufacturing and operating the same

SOI protection for buried plate implant and DT bottle ETCH

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed

Charge breakdown avoidance for MIM elements in SOI base technology and method

SEMICONUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Device Having a Floating Body Transistor and Method for Manufacturing the Same

Trench memory with self-aligned strap formed by self-limiting process

Semiconductor Device and Method for Manufacturing the Same

Method and resultant structure for floating body memory on bulk wafer

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Method of fabricating PMOS and NMOS transistor on the same substrate

Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device

Semiconductor device comprising a metal gate stack of reduced height and method of forming the same

CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS

Modified hybrid orientation technology

SOI device having an increasing charge storage capacity of transistor bodies and method for manufacturing the same

SOI devices

Semiconductor device structures and methods of forming semiconductor structures

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

High-Z structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels

Semiconductor device and method of manufacturing the same

SOI field effect transistor with a back gate for modulating a floating body

Super hybrid SOI CMOS devices

Semiconductor devices and semiconductor apparatuses including the same

Hybrid orientation scheme for standard orthogonal circuits

Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same

Semiconductor device having SOI structure

Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE USING ELEMENT ISOLATION REGION OF TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

Vertical system integration

Manufacturing method of semiconductor substrate

Capacitorless DRAM on bulk silicon

Heat transfer film, semiconductor device, and electronic apparatus

Semiconductor memory device

Structure and method for improved SRAM interconnect

Method for forming strained channel PMOS devices and integrated circuits therefrom

Anisotropic stress generation by stress-generating liners having a sublithographic width

SOI semiconductor components and methods for their fabrication

Silicon on insulator device and method for fabricating the same

Flash memory cell string

SOI BASED INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING

Deep trench capacitor in a SOI substrate having a laterally protruding buried strap

Method for manufacturing a semiconductor substrate by laser irradiation

Methods of forming semiconductor devices having self-aligned bodies

Methods of designing an integrated circuit on corrugated substrate

Protection against charging damage in hybrid orientation transistors

Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits

Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures

SEMICONDUCTOR SUBSTRATE MANUFACTURING APPARATUS

Hybrid orientation substrate compatible deep trench capacitor embedded DRAM

Fully-depleted (FD)(SOI) MOSFET access transistor and method of fabrication

Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode

Semiconductor substrate, method of fabricating the same, method of fabricating semiconductor device, and method of fabricating image sensor

SEMICONDUCTOR DEVICE HAVING FIN TRANSISTOR AND PLANAR TRANSISTOR AND ASSOCIATED METHODS OF MANUFACTURE

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

Hetero-junction bipolar transistor (HBT) and structure thereof

STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER

Hybrid Wafers

Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

Method of preparing active silicon regions for CMOS or other devices

CMOS transistor and method for manufacturing the same

Method for manufacturing semiconductor device

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Lateral bipolar transistor

Semiconductor device

Semiconductor device heat dissipation structure

Method of fabricating multi-gate semiconductor devices with improved carrier mobility

Semiconductor device and manufacturing method of semiconductor device

Semiconductor on insulator (SOI) switching circuit

Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C

Grounding front-end-of-line structures on a SOI substrate

Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication

Independently controlled, double gate nanowire memory cell with self-aligned contacts

Hybrid semiconductor structure

MASKLESS STRESS MEMORIZATION TECHNIQUE FOR CMOS DEVICES

Memory array having a programmable word length, and method of operating same

Method of fabricating patterned SOI devices and the resulting device structures

Integrated circuit having memory cell array including barriers, and method of manufacturing same

Semiconductor storage device and manufacturing method thereof

Semiconductor device including SRAM

Semiconductor device and method for controlling semiconductor device

Fin-type field effect transistor and semiconductor device

SEMICONDUCTOR MEMORY

In-line light sensor

Method for fabricating isolated integrated semiconductor structures

Semiconductor device having SOI substrate and method for manufacturing the same

Zero capacitor RAM with reliable drain voltage application and method for manufacturing the same

Semiconductor device and method for manufacturing the same

Method of manufacturing a semiconductor device including a semiconductor substrate with stripes of different crystal plane directions

Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate

Semiconductor device with high-breakdown-voltage transistor

DUAL WIRED INTEGRATED CIRCUIT CHIPS

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Double-sided integrated circuit chips

EEPROM and method of manufacturing the same

Semiconductor device

Floating body memory cell system and method of manufacture

IMAGE DISPLAY APPARATUS USING THIN-FILM TRANSISTORS

Transient voltage suppressor manufactured in silicon on oxide (SOI) layer

Semiconductor memory device and manufacturing method thereof

Semiconductor device including a plurality of memory cells with no difference in erasing properties

CMOS EPROM and EEPROM devices and programmable CMOS inverters

Manufacturing method of SOI substrate

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors

CMOS structure and method including multiple crystallographic planes

SOI device having a substrate diode formed by reduced implantation energy

Semiconductor memory having both volatile and non-volatile functionality and method of operating

Determining history state of data in data retaining device based on state of partially depleted silicon-on-insulator

SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE

Semiconductor device and method for fabricating the same

Semiconductor device

SOI CMOS circuits with substrate bias

High-performance FET device layout

Semiconductor memory having both volatile and non-volatile functionality and method of operating

Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors

Multiple crystallographic orientation semiconductor structures

Semiconductor device having a plurality of elements on one semiconductor substrate and method of manufacturing the same

One-transistor cell semiconductor on insulator random access memory

Electronically scannable multiplexing device

PROCESS FOR FABRICATING A FIELD-EFFECT TRANSISTOR WITH DOPING SEGREGATION USED IN SOURCE AND/OR DRAIN

Semiconductor device and method for manufacturing the same

Non-volatile memory device, method of operating the same, and method of fabricating the same

Semiconductor device and method for manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same

Semiconductor storage device and manufacturing method thereof

BONDED SOI SUBSTRATE, AND METHOD FOR MANUFACTURING THE SAME

SOI SUBSTRATE CONTACT WITH EXTENDED SILICIDE AREA

SOI substrate contact with extended silicide area

Electronic device and method of biasing

METHOD OF FORMING HIGH-K GATE ELECTRODE STRUCTURES AFTER TRANSISTOR FABRICATION

Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells

Method for manufacturing semiconductor substrate and semiconductor device

Shallow trench isolation structure compatible with SOI embedded DRAM

Stress enhanced semiconductor device and methods for fabricating same

NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor device and method of fabricating the same

SEMICONDUCTOR DEVICE AND ELECTRONIC APPLIANCE

HARDENED TRANSISTORS IN SOI DEVICES

Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS

SOI CMOS compatible multiplanar capacitor

Structures having lattice-mismatched single-crystalline semiconductor layers on the same lithographic level and methods of manufacturing the same

Method and structures for accelerated soft-error testing

Metal high-K transistor having silicon sidewall for reduced parasitic capacitance, and process to fabricate same

NON-VOLATILE MEMORY DEVICES

Semiconductor memory device and method of manufacturing the same

NAND type nonvolatile semiconductor memory device having sideface electrode shared by memory cells

METHOD FOR MANUFACTURING A SEMICONDUCTOR ARRANGEMENT, USE OF A TRENCH STRUCTURE, AND SEMICONDUCTOR ARRANGEMENT

METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY

MICROCHIP AND SOI SUBSTRATE FOR MANUFACTURING MICROCHIP

Integrated circuit and method of manufacturing an integrated circuit

Method of forming CMOS device having gate insulation layers of different type and thickness

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE

Inverted nonvolatile memory device, stack module, and method of fabricating the same

Semiconductor device and methods for fabricating same

Manufacturing method of semiconductor device, semiconductor device, and electronic device

Semiconductor device

Method for fabricating nanocoils

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND RESISTOR

Semiconductor device

Semiconductor device and the method of manufacturing the same

Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Bipolar transistor FINFET technology

Ultrathin SOI CMOS devices employing differential STI liners

Method of selective oxygen implantation to dielectrically isolate semiconductor devices using no extra masks

Low crosstalk substrate for mixed-signal integrated circuits

Semiconductor device including a film for applying stress to a channel formation region to increase current flow

Semiconductor device and method for fabricating the same

Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs

Hybrid orientation CMOS with partial insulation process

Method for integrating silicon-on-nothing devices with standard CMOS devices

METHOD FOR FORMING A DEEP TRENCH IN AN SOI DEVICE BY REDUCING THE SHIELDING EFFECT OF THE ACTIVE LAYER DURING THE DEEP TRENCH ETCH PROCESS

Process for making a semiconductor device using partial etching

Hybrid orientation substrate and method for fabrication thereof

NOR-type channel-program channel-erase contactless flash memory on SOI

Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof

Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device

Integrated circuit employing variable thickness film

Integrated circuit including a semiconductor assembly in thin-SOI technology

Vertical floating body cell of a semiconductor device and method for fabricating the same

Capacitorless DRAM and methods of operating the same

Manufacturing method of a semiconductor device including a single crystal semiconductor film, and a semiconductor film including impurity

Liquid Washing or Cleaning Composition Comprising Particulate Peracid Bleach

Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate

Semiconductor memory device manufacturing method and semiconductor memory device

Semiconductor device and method for manufacturing the same

FinFET SRAM with asymmetric gate and method of manufacture thereof

Semiconductor device and method of manufacturing the same

Lateral Power MOSFET With Integrated Schottky Diode

DIRECT BOND SUBSTRATE OF IMPROVED BONDED INTERFACE HEAT RESISTANCE

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF AND SEMICONDUCTOR INTEGRATED CIRCUIT

Method of fabricating a metal gate CMOS with at least a single gate metal and dual gate dielectrics

Protective bumper adapted for minimizing damage to materials carried by a materials handling vehicle

Semiconductor device with three-dimensional field effect transistor structure

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer

SRAM device

Method of manufacturing semiconductor storage device

Semiconductor switching devices and fabrication methods

Fiber Soi Substrate, Semiconductor Device Using Same and Method for Manufacturing Same

SILICON PHOTODETECTOR AND METHOD FOR FORMING THE SAME

Reducing transistor junction capacitance by recessing drain and source regions

TRANSISTOR HAVING REDUCED GATE RESISTANCE AND ENHANCED STRESS TRANSFER EFFICIENCY AND METHOD OF FORMING THE SAME

Stress enhanced MOS circuits

Method of forming an SOI substrate contact

Method of forming a guard ring or contact to an SOI substrate

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology

Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate

Method for fabricating semiconductor device and semiconductor device with separation along peeling layer

SOI device with charging protection and methods of making same

Method of manufacturing a plurality of semiconductor devices and carrier substrate

Method of manufacturing semiconductor substrate with reduced gap size between single-crystalline layers

Semiconductor device

Semiconductor device and manufacturing method of the semiconductor device

Semiconductor device, method of manufacturing same and method of designing same

HIGH K DIELECTRIC MATERIALS INTEGRATED INTO MULTI-GATE TRANSISTOR STRUCTURES

Front and backside processed thin film electronic devices

Method and structure for self-aligned device contacts

CMOS transistors with differential oxygen content high-k dielectrics

Transistor with reduced charge carrier mobility

METHOD FOR FABRICATING AN SOI DEFINED SEMICONDUCTOR DEVICE

Memory structure and method of making the same

Method for manufacturing NAND-type semiconductor storage device

Silicon on insulator (SOI) wafer and process for producing same

Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor

Super hybrid SOI CMOS devices

Integrated circuit system with triode

Back-side trapped non-volatile memory device

Dual work-function single gate stack

Silicon on insulator (SOI) wafer and process for producing same

Liquid crystal display device and its manufacturing method

Semiconductor substrate and manufacturing method of semiconductor device

MOS structures with remote contacts and methods for fabricating the same

Semiconductor memory device and manufacturing method thereof

Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels

Electronic device including a transistor structure having an active region adjacent to a stressor layer

Released freestanding strained heterojunction structures

Nanosilicon semiconductor substrate manufacturing method and semiconductor circuit device using nanosilicon semiconductor substrate manufactured by the method

Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions

Semiconductor device having a fin structure and method of manufacturing the same

MULTIPLE WAFER LEVEL MULTIPLE PORT REGISTER FILE CELL

Silicon-on-insulator structures for through via in silicon carriers

Integrated circuit on corrugated substrate

Electrical fuse with metal silicide pipe under gate electrode

Semiconductor device with a plurality of isolated conductive films

Memory cell

Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer

Semiconductor device manufacturing methods

Vertical system integration

Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit

Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates

Single and double-gate pseudo-FET devices for semiconductor materials evaluation

Non-volatile semiconductor storage device and manufacturing method thereof

Semiconductor device

Memory device and semiconductor device

Methods of forming memory arrays and semiconductor constructions

Method of manufacturing a semiconductor device with a gate electrode having a laminate structure

Residue free patterned layer formation method applicable to CMOS structures

Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor memory device and manufacturing method thereof

Semiconductor device and method of manufacturing the same

Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation

Step height reduction between SOI and EPI for DSO and BOS integration

Formation of dummy features and inductors in semiconductor fabrication

Dual metal gates for mugfet device

SONOS memory device with reduced short-channel effects

Semiconductor storage element and manufacturing method thereof

Conductive spacers for semiconductor devices and methods of forming

Enhancing transistor characteristics by a late deep implantation in combination with a diffusion-free anneal process

Stacking fault reduction in epitaxially grown silicon

SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device

Integrated circuits and power supplies

High power device isolation and integration

BUILDING FULLY-DEPLETED AND BULK TRANSISTORS ON SAME CHIP

Semiconductor layer structure and method of making the same

BUILDING FULLY-DEPLETED AND PARTIALLY-DEPLETED TRANSISTORS ON SAME CHIP

Non-Volatile Memory Device Having a Gap in the Tunnuel Insulating Layer and Method of Manufacturing the Same

Hybrid fin field-effect transistor structures and related methods

Methods for fabricating a stress enhanced semiconductor device having narrow pitch and wide pitch transistors

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor layer structure and method of making the same

Method for manufacturing SOI substrate and semiconductor device

Method of manufacturing SOI substrate

Separate layer formation in a semiconductor device

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation