Method of making a semiconductor device using a stressor

Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner

Method of making a semiconductor device with a stressor

Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices

Methods of forming a material film, methods of forming a capacitor, and methods of forming a semiconductor memory device using the same

Trench structure and method of forming trench structure

Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer

Stacked SONOS memory

Hybrid substrates and methods for forming such hybrid substrates

Stressed MOS device

Strained silicon CMOS on hybrid crystal orientations

Fabrication process for silicon-on-insulator field effect transistors using high temperature nitrogen annealing

SOI semiconductor device with body contact and method thereof

Vertical system integration

Vertical system integration

MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER

P-Channel FET Whose Hole Mobility is Improved by Applying Stress to the Channel Region and a Method of Manufacturing the Same

Electronically scannable multiplexing device

Semiconductor storage device and driving method thereof

Apparatus of memory array using FinFETs

Method for manufacturing semiconductor substrate

Integration of strained Ge into advanced CMOS technology

CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates

ELECTRONIC DEVICE AND METHOD

SOI substrate, method for manufacturing the same, and semiconductor device

Device fabrication by anisotropic wet etch

Method for forming multi-gate non-volatile memory devices using a damascene process

Method for manufacturing semiconductor device

Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations

Method of fabricating non-volatile memory device

Semiconductor memory device

SOI substrate and method for manufacturing SOI substrate

SOI substrate and method for manufacturing SOI substrate

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor device with bipolar transistor

Patterned backside stress engineering for transistor performance optimization

METHODS OF FORMING HIGHLY ORIENTED DIAMOND FILMS AND STRUCTURES FORMED THEREBY

Fully Depleted SOI Multiple Threshold Voltage Application

Manufacturing process for zero-capacitor random access memory circuits

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

After gate fabrication of field effect transistor having tensile and compressive regions

Structure and method for strained transistor directly on insulator

Vertical system integration

Method and structure for self-aligned device contacts

Semiconductor memory device and manufacturing process therefore

Nonvolatile semiconductor memory device

Methods of forming vertical transistors

Semiconductor device

SUBGROUND RULE STI FILL FOR HOT STRUCTURE

TRANSISTORS HAVING V-SHAPE SOURCE/DRAIN METAL CONTACTS

STRAINED HOT (HYBRID OREINTATION TECHNOLOGY) MOSFETs

Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates

Electrostatic discharge protection device and method of fabricating same

Deep STI trench and SOI undercut enabling STI oxide stressor

Fabrication method of a mixed substrate and use of the substrate for producing circuits

Defect-free hybrid orientation technology for semiconductor devices

Method for preparing 2-dimensional semiconductor devices for integration in a third dimension

Semiconductor device having tiles for dual-trench integration and method therefor

Trench formation in a semiconductor material

Heterogeneous Semiconductor Substrate

ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION

Dual wired integrated circuit chips

Semiconductor memory device

Method of forming a semiconductor structure

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Forming a semiconductor device having epitaxially grown source and drain regions

Forming semiconductor fins using a sacrificial fin

Semiconductor fin integration using a sacrificial fin

Technique for patterning differently stressed layers formed above transistors by enhanced etch control strategies

Semiconductor memory device and method of operating same

Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates

Semiconductor substrate, semiconductor device, method for manufacturing semiconductor substrate, and method for manufacturing semiconductor device

FIELD EFFECT TRANSISTOR ARRANGEMENT AND METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT

Semiconductor device

NROM flash memory devices on ultrathin silicon

Hybrid orientation SOI substrates, and method for forming the same

Demultiplexers using transistors for accessing memory cell arrays

Semiconductor device having a strained semiconductor alloy concentration profile

SEMICONDUCTOR INTEGRATED CIRCUIT

Methods of forming semiconductor constructions

SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2

Electronic device, method for manufacturing the same, and silicon substrate for electronic device

Semiconductor structure including gate electrode having laterally variable work function

Stressed SOI FET having tensile and compressive device regions

Semiconductor structure and method of forming the structure

Thin Film Semiconductor Device and Method for Manufacturing the Same

Buried stress isolation for high-performance CMOS technology

Semiconductor substrate with multiple crystallographic orientations

Silicon-on-insulator (“SOI”) transistor test structure for measuring body-effect

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

Electronic device including insulating layers having different strains

Two-sided semiconductor-on-insulator structures and methods of manufacturing the same

Semiconductor storage device and manufacturing method thereof

SEMICONDUCTOR MEMORY DEVICE

Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate

Strained MOS devices using source/drain epitaxy

MOSFET on SOI device

Access device having vertical channel and related semiconductor device and a method of fabricating the access device

Memory having a vertical access device

Low-cost strained SOI substrate for high-performance CMOS technology

Method for forming SOI device

Subground rule STI fill for hot structure

Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer

Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory

Self-aligned body contact for a semiconductor-on-insulator trench device and method of fabricating same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor device and electronic device having the same

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

Integrated assist features for epitaxial growth bulk tiles with compensation

Semiconductor device

Shallow trench isolation process utilizing differential liners

Structure and method for MOSFET gate electrode landing pad

DYNAMIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD THEREOF

Light erasable memory and method therefor

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Silicon-on-insulator chip with multiple crystal orientations

System for fabrication of integrated tunable/switchable passive microwave and millimeter wave modules

Trench structure and method for co-alignment of mixed optical and electron beam lithographic fabrication levels

Methods of forming semiconductor devices with extended active regions

Method for co-alignment of mixed optical and electron beam lithographic fabrication levels

Semiconductor device, method of controlling the same, and method of manufacturing the same

Convex shaped thin-film transistor device

Method of combining floating body cell and logic transistors

Method for manufacturing a SOI substrate associating silicon based areas and GaAs based areas

Method and resultant structure for floating body memory on bulk wafer

Semiconductor device including an active region and two layers having different stress characteristics

Semiconductor memory and manufacturing method thereof

Flash NAND memory cell array with charge storage elements positioned in trenches

Method for manufacturing semiconductor device

Crystal imprinting methods for fabricating substrates with thin active silicon layers

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME

Floating body memory and method of fabricating the same

MOS TRANSISTOR, METHOD FOR MANUFACTURING THE MOS TRANSISTOR, CMOS SEMICONDUCTOR DEVICE INCLUDING THE MOS TRANSISTOR, AND SEMICONDUCTOR DEVICE INCLUDING THE CMOS SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS

NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same

Method for fabricating SOI device

Semiconductor memory device

Semiconductor storage unit, semiconductor device and display device as well as liquid crystal display and image receiving apparatus

Device patterned with sub-lithographic features with variable widths

Embedded substrate interconnect for underside contact to source and drain regions

Semiconductor device and manufacturing method thereof

Relaxed low-defect SGOI for strained SI CMOS applications

Semiconductor device

Semiconductor Device and Manufacturing Method Thereof

Dual wired integrated circuit chips

Semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device fabrication method and semiconductor device

Semiconductor substrate including a plurality of insulating regions, semiconductor device having the same, and method of manufacturing the device

Methods for forming III-V semiconductor device structures

Process of forming an electronic device including a conductive structure extending through a buried insulating layer

Methods for fabricating a semiconductor device on an SOI substrate

Methods of forming vertical transistors

SELECTIVE STRESS RELAXATION BY AMORPHIZING IMPLANT IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT

Reducing Crystal Defects from Hybrid Orientation Technology During Semiconductor Manufacture

Electronic device including a conductive structure extending through a buried insulating layer

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TRANSISTOR HAVING SOURCE/DRAIN REGION ONLY UNDER SIDEWALL SPACER EXCEPT FOR CONTACTS AND METHOD

Stress enhanced CMOS circuits and methods for their fabrication

Nonvolatile memory cell, array thereof, fabrication methods thereof and device comprising the same

Memory device and semiconductor device

Semiconductor device, logic circuit and electronic equipment

CMOS structure including topographic active region

Semiconductor device

Method of enhancing hole mobility

Poly filled substrate contact on SOI structure

Hybrid orientation substrate and method for fabrication of thereof

Integration of a floating body memory on SOI with logic transistors on bulk substrate

HYBRID CRYSTALLOGRAPHIC SURFACE ORIENTATION SUBSTRATE HAVING ONE OR MORE SOI REGIONS AND/OR BULK SEMICONDUCTOR REGIONS

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Nonvolatile semiconductor memory device and method for manufacturing the same

Electronic device including a heterojunction region

Method of providing protection against charging damage in hybrid orientation transistors

Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers

Process charging and electrostatic damage protection in silicon-on-insulator technology

FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

Structure and method of fabricating FinFET with buried channel

Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels

Method of fabricating vertical body-contacted SOI transistor

SOI BIPOLAR TRANSISTORS WITH REDUCED SELF HEATING

Semiconductor device including storage device and method for driving the same

SEMICONDUCTOR DEVICE AND MANFACTURING METHOD OF THE SAME

Integrated circuits

Ultra-thin oxide bonding for S1 to S1 dual orientation bonding

High-performance CMOS SOI devices on hybrid crystal-oriented substrates

Semiconductor device

Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using SOI wafers

Semiconductor device including antenna

Semiconductor device and method for fabricating a semiconductor device

Decoder for a stationary switch machine

Dual work-function single gate stack

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

Self-aligned strap for embedded trench memory on hybrid orientation substrate

MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness

Memory devices and memory systems having the same

Enhanced mobility MOSFET devices

SOI semiconductor components and methods for their fabrication

Bottom-gate sonos-type cell having a silicide gate

Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same

Field effect transistor comprising a stressed channel region and method of forming the same

Strained Si/SiGe/SOI islands and processes of making same

High-voltage MOS device improvement by forming implantation regions

Semiconductor device

Semiconductor memory and method for manufacturing a semiconductor memory

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Methods to create dual-gate dielectrics in transistors using high-K dielectric

Semiconductor device

Electronically scannable multiplexing device

Semiconductor device

Semiconductor device and manufacturing method of the same

Method for producing multi-gate field-effect transistor with fin structure having drain-extended MOS field-effect transistor

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C

Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates

Apparatus and methods for multi-gate silicon-on-insulator transistors

Semiconductor device

Field effect transistor (FET) devices and methods of manufacturing FET devices

Semiconductor device using Filled Tetrahedral semiconductor

Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates

Semiconductor device with under-filled heat extractor

Method for fabricating semiconductor device

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY

Semiconductor device

Method of manufacturing semiconductor device having impurity region under isolation region

Semiconductor structure with enhanced performance using a simplified dual stress liner configuration

Demultiplexers using transistors for accessing memory cell arrays

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates

Method of manufacturing semiconductor device having impurity region under isolation region

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

Buried decoupling capacitors, devices and systems including same, and methods of fabrication

Element formation substrate, method of manufacturing the same, and semiconductor device

Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor system using germanium condensation

Low-cost high-performance planar back-gate CMOS

SINGLE AND DOUBLE-GATE PSEUDO-FET DEVICES FOR SEMICONDUCTOR MATERIALS EVALUATION

THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN

Semiconductor device and method for manufacturing the same

Method for fabricating stress enhanced MOS circuits

Strained MOSFETs on separated silicon layers

Pseudo SOI substrate and associated semiconductor devices

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

System for displaying images including thin film transistor device and method for fabricating the same

Thin film transistor array panel and method of manufacturing the same

Semiconductor memory device having a floating body and a plate electrode

Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit

Programmable random logic arrays using PN isolation

Void formation for semiconductor junction capacitance reduction

Semiconductor device with fin-type field effect transistor and manufacturing method thereof.

Selective silicon-on-insulator isolation structure and method

Process for integrating on an inert substrate a device comprising at least a passive element and an active element and corresponding integrated device

Semiconductor-on-insulator (SOI) strained active area transistor

Semiconductor device

Semiconductor method and device with mixed orientation substrate

Semiconductor structure with self-aligned device contacts

INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF

Semiconductor device and method for manufacturing thereof

Semiconductor memory device and manufacturing method of the same

Semiconductor device having fin-field effect transistor and manufacturing method thereof

Semiconductor memory device and manufacturing method of the same

Memory element and semiconductor device

Method of manufacturing a semiconductor device and a non-volatile semiconductor storage device including the formation of an insulating layer using a plasma treatment

Process for controlling performance characteristics of a negative differential resistance (NDR) device

Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETS

Front-rear contacts of electronics devices with induced defects to increase conductivity thereof

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device with channel layer comprising different types of impurities

SOI device and method for its fabrication

Vertical-type, integrated bipolar device and manufacturing process thereof

Low cost high density rectifier matrix memory

Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit

Selective oxidation of silicon in diode, TFT and monolithic three dimensional memory arrays

Low cost high density rectifier matrix memory

Semiconductor component including an isolation structure and a contact to the substrate

Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer

Semiconductor device to suppress leak current at an end of an isolation film

SOI Device with charging protection and methods of making same

Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells

Liquid crystal display device and electronic device

Stacking fault reduction in epitaxially grown silicon

Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment

Selective formation of stress memorization layer

Semiconductor device and driving method therefor

Semiconductor device and electronic device

Liquid crystal display device and method for fabricating the same

Hybrid Field Effect Transistor and Bipolar Junction Transistor Structures and Methods for Fabricating Such Structures

Semiconductor memory device and method of manufacturing the same

Method of making metal gate transistors

SOI devices and methods for fabricating the same

CMOS devices with stressed channel regions, and methods for fabricating the same

Semiconductor device fabrication method

Epitaxy silicon on insulator (ESOI)

Nonvolatile semiconductor memory