ClassID:

209385

H01L2224/0214 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area Structure of the auxiliary member

Recent Application in this class:
#1
20250311466
2025-10-02

SEMICONDUCTOR DEVICE

#2
20250157955
2025-05-15

WAFER LEVEL PACKAGE WITH POLYMER LAYER DELAMINATION PREVENTION DESIGN AND METHOD OF FORMING THE SAME

#3
20250140718
2025-05-01

DIELECTRIC-FILLED BOND PADS IN CLIP PACKAGES

#4
20240136383
2024-04-25

SEMICONDUCTOR DEVICE

#5
20240055379
2024-02-15

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME

#6
20240030104
2024-01-25

SEMICONDUCTOR PACKAGES

#7
20230122531
2023-04-20

REDUCED PARASITIC CAPACITANCE IN BONDED STRUCTURES

#8
20230056623
2023-02-23

Semiconductor redistribution structure with integrated test pad and method for preparing the same

#9
20230036317
2023-02-02

Wafer level package with polymer layer delamination prevention design and method of forming the same

#10
20220102245
2022-03-31

Semiconductor packages

#11
20220084966
2022-03-17

BONDING PAD STRUCTURE, SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR PREPARING SAME

#12
20220077217
2022-03-10

Semiconductor device

#13
20210225787
2021-07-22

Redistribution layer (RDL) structure, semiconductor device and manufacturing method thereof

#14
20190348382
2019-11-14

Stress relieving structure for semiconductor device

#15
20190259800
2019-08-22

CMOS sensors and methods of forming the same

#16
20190140010
2019-05-09

CMOS sensors and methods of forming the same

#17
20170221845
2017-08-03

Packaging devices and methods of manufacture thereof

#18
20170162540
2017-06-08

Wafer-level chip-scale package with redistribution layer

#19
20170148752
2017-05-25

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

#20
20170033064
2017-02-02

Packaging devices and methods of manufacture thereof

#21
20170018525
2017-01-19

METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS

#22
20160372436
2016-12-22

Concentric bump design for the alignment in die stacking

#23
20160351518
2016-12-01

Packaging devices and methods of manufacture thereof

#24
20150243613
2015-08-27

Packaging devices and methods of manufacture thereof

#25
20150179605
2015-06-25

Method for aligning micro-electronic components

#26
20130256877
2013-10-03

Semiconductor package

#27
20080128905
2008-06-05

Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package

#28
20050255686
2005-11-17

Method of manufacturing semiconductor device