ClassID:

209381

H01L2224/02123 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area

Sub-classes:
Recent Application in this class:
#1
20200185343
2020-06-11

Semiconductor device and method of manufacturing a semiconductor device

#2
20180269171
2018-09-20

Semiconductor device and method of manufacturing a semiconductor device

#3
20180269170
2018-09-20

Semiconductor device and method of manufacturing a semiconductor device

#4
20180090394
2018-03-29

Pressure-activated electrical interconnection by micro-transfer printing

#5
20170287789
2017-10-05

Pressure-activated electrical interconnection by micro-transfer printing

#6
20160218073
2016-07-28

Semiconductor device

#7
20140144690
2014-05-29

Method for producing a structure for microelectronic device assembly

#8
20140061900
2014-03-06

Semiconductor package with improved redistribution layer design and fabricating method thereof

#9
20130009286
2013-01-10

SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME

#10
20120211900
2012-08-23

Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer

#11
20120146210
2012-06-14

Compliant interconnects in wafers

#12
20110171822
2011-07-14

Method of manufacturing an interconnect structure for a semiconductor device

#13
20110079897
2011-04-07

Integrated circuit chip and flip chip package having the integrated circuit chip

#14
20100244267
2010-09-30

Interconnect structure for a semiconductor device

#15
20100105200
2010-04-29

Semiconductor package with passivation island for reducing stress on solder bumps

#16
20090079070
2009-03-26

Semiconductor package with passivation island for reducing stress on solder bumps

#17
20080048312
2008-02-28

Semiconductor package and method for manufacturing the same

#18
20070085219
2007-04-19

Method for manufacture of wafer level package with air pads

#19
20060278984
2006-12-14

Semiconductor device with a diffusion barrier film having a spacing for stress relief of solder bump

#20
20060202314
2006-09-14

Semiconductor package and method for manufacturing the same

#21
20050040528
2005-02-24

Method of arranging microspheres with liquid, microsphere arranging device, and semiconductor device