Patents-Review.com
ClassID:

209389 ⎘

H01L2224/02165 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area Reinforcing structures

Recent Application in this class:
#1
20250349772
2025-11-13

SEMICONDUCTOR STRUCTURE, PACKAGE STRUCTURE AND MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

 #2
20250105177
2025-03-27

SEMICONDUCTOR DEVICE

 #3
20240234351
2024-07-11

ELECTRICAL CONNECTION AND FORMING METHOD THEREOF

 #4
20240136313
2024-04-25

ELECTRICAL CONNECTION AND FORMING METHOD THEREOF

 #5
20230420388
2023-12-28

SEMICONDUCTOR STRUCTURES INCLUDING AUXETIC MICROSTRUCTURES AND METHOD OF FORMING THE SAME

 #6
20230352430
2023-11-02

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

 #7
20210305174
2021-09-30

Semiconductor device

 #8
20210119414
2021-04-22

Semiconductor devices and methods for producing the same

 #9
20200043876
2020-02-06

Adhesion Enhancing Structures for a Package

 #10
20190304932
2019-10-03

Guard ring method for semiconductor devices

 #11
20180197807
2018-07-12

Semiconductor device

 #12
20170084560
2017-03-23

Methods and apparatus for solder connections

 #13
20170012005
2017-01-12

Guard ring method for semiconductor devices

 #14
20160307863
2016-10-20

Semiconductor package

 #15
20150214168
2015-07-30

Substrate structure and fabrication method thereof

 #16
20140361433
2014-12-11

SEMICONDUCTOR DEVICE

 #17
20140239496
2014-08-28

Semiconductor device and method of forming micro-vias partially through insulating material around bump interconnect

 #18
20140131859
2014-05-15

Solder fatigue arrest for wafer level package

 #19
20130277838
2013-10-24

Methods and apparatus for solder connections

 #20
20130270710
2013-10-17

Guard ring design structure for semiconductor devices

 #21
20130249105
2013-09-26

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

 #22
20130147031
2013-06-13

Semiconductor device with bump structure on an interconncet structure

 #23
20120282728
2012-11-08

Backside illuminated imaging sensor with reinforced pad structure

 #24
20120273937
2012-11-01

Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer Layer

 #25
20120267779
2012-10-25

SEMICONDUCTOR PACKAGE

 #26
20120032324
2012-02-09

Semiconductor device having a conductive layer reliably formed under an electrode pad

 #27
20110143531
2011-06-16

Packaging conductive structure and method for manufacturing the same

 #28
20110115002
2011-05-19

Backside illuminated imaging sensor with reinforced pad structure

 #29
20090160052
2009-06-25

UNDER BUMP METALLURGY STRUCTURE OF SEMICONDUCTOR DEVICE PACKAGE

 #30
20080197489
2008-08-21

Packaging conductive structure and method for manufacturing the same

 #31
20070176290
2007-08-02

Wafer level chip scale package having a gap and method for manufacturing the same

 #32
20070013065
2007-01-18

Semiconductor device

 #33
20060214293
2006-09-28

Wafer level chip scale package having a gap and method for manufacturing the same

 #34
20060166402
2006-07-27

Elevated bond-pad structure for high-density flip-clip packaging and a method of fabricating the structures

 #35
15186100
2017-11-07

Chip package and a manufacturing method thereof