Patents-Review.com
ClassID:

209429 ⎘

H01L2224/03001 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Manufacturing methods Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate

Sub-classes:
Recent Application in this class:
#1
20260026315
2026-01-22

SACRIFICIAL PAD DESIGN FOR SEMICONDUCTOR DEVICE

 #2
20250293186
2025-09-18

BOND PAD STRUCTURE COUPLED TO MULTIPLE INTERCONNECT CONDUCTIVE\ STRUCTURES THROUGH TRENCH IN SUBSTRATE

 #3
20250239547
2025-07-24

SEMICONDUCTOR DEVICE STRUCTURE HAVING HYBRID BOND STRUCTURE WITH AIR GAP AND METHOD OF MANUFACTURING THE SAME

 #4
20250239546
2025-07-24

SEMICONDUCTOR DEVICE STRUCTURE HAVING HYBRID BOND STRUCTURE WITH AIR GAP AND METHOD OF MANUFACTURING THE SAME

 #5
20250239544
2025-07-24

SEMICONDUCTOR DEVICE STRUCTURE HAVING HYBRID BOND STRUCTURE WITH AIR GAP AND METHOD OF MANUFACTURING THE SAME

 #6
20250105180
2025-03-27

Semiconductor Device And Method Of Manufacturing The Same

 #7
20240387297
2024-11-21

SEMICONDUCTOR STRUCTURE AND TEST METHOD THEREOF

 #8
20240363561
2024-10-31

INTEGRATED CIRCUIT FEATURES WITH OBTUSE ANGLES AND METHOD OF FORMING SAME

 #9
20240274554
2024-08-15

Semiconductor device with composite conductive features and method for fabricating the same

 #10
20240250047
2024-07-25

Semiconductor device with composite conductive features and method for fabricating the same

 #11
20240162175
2024-05-16

SEMICONDUCTOR PACKAGE OR DEVICE WITH BARRIER LAYER

 #12
20240120298
2024-04-11

SEMICONDUCTOR DIE HAVING AN OPTICAL DETECTION MARKER AND METHOD OF PRODUCING THE SEMICONDUCTOR DIE

 #13
20240006351
2024-01-04

SELECTIVE PLATING FOR PACKAGED SEMICONDUCTOR DEVICES

 #14
20230395540
2023-12-07

BOND PAD STRUCTURE COUPLED TO MULTIPLE INTERCONNECT CONDUCTIVE\ STRUCTURES THROUGH TRENCH IN SUBSTRATE

 #15
20230299023
2023-09-21

Semiconductor device with composite conductive features and method for fabricating the same

 #16
20230116270
2023-04-13

Integrated circuit features with obtuse angles and method of forming same

 #17
20230026305
2023-01-26

Semiconductor device and method of manufacturing the same

 #18
20220367296
2022-11-17

Integrated circuit test method and structure thereof

 #19
20220344291
2022-10-27

Bond pad structure coupled to multiple interconnect conductive\ structures through trench in substrate

 #20
20220173000
2022-06-02

MANUFACTURING METHOD OF PACKAGE CIRCUIT

 #21
20220102300
2022-03-31

Semiconductor device and method for manufacturing semiconductor device

 #22
20220028748
2022-01-27

Integrated circuit test method and structure thereof

 #23
20210225679
2021-07-22

Transfer printing method and transfer printing apparatus

 #24
20210074656
2021-03-11

Integrated circuit features with obtuse angles and method of forming same

 #25
20200331750
2020-10-22

METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING CAVITIES FILLED WITH A SACRIFICIAL MATERIAL

 #26
20200161260
2020-05-21

Integrated circuit features with obtuse angles and method forming same

 #27
20200010970
2020-01-09

Copper electroplating compositions and methods of electroplating copper on substrates

 #28
20190136396
2019-05-09

Copper electroplating compositions and methods of electroplating copper on substrates

 #29
20190136395
2019-05-09

Copper electroplating compositions and methods of electroplating copper on substrates

 #30
20190131265
2019-05-02

Chip package assembly with enhanced interconnects and method for fabricating the same

 #31
20190057931
2019-02-21

PACKAGE METHOD FOR GENERATING PACKAGE STRUCTURE WITH FAN-OUT INTERFACES

 #32
20180269124
2018-09-20

Semiconductor package device

 #33
20170317045
2017-11-02

Manufacturing method of semiconductor package

 #34
20170210617
2017-07-27

Methods of fabricating semiconductor structures including cavities filled with a sacrificial material

 #35
20170179056
2017-06-22

Semiconductor device with a bump contact on a TSV comprising a cavity and method of producing such a semiconductor device

 #36
20170011981
2017-01-12

Semiconductor package device and manufacturing method thereof

 #37
20160372430
2016-12-22

Conductive pillar shaped for solder confinement

 #38
20160163664
2016-06-09

Semiconductor substrate and manufacturing method thereof

 #39
20160099222
2016-04-07

Integrated circuit packaging system with under bump metallization and method of manufacture thereof

 #40
20150325507
2015-11-12

Conductive connections, structures with such connections, and methods of manufacture

 #41
20150279794
2015-10-01

Semiconductor chip with patterned underbump metallization and polymer film

 #42
20150214169
2015-07-30

Method of fabricating connection structure for a substrate

 #43
20150064877
2015-03-05

Methods for processing a semiconductor wafer

 #44
20140248730
2014-09-04

MEMS device and method of formation thereof

 #45
20140138833
2014-05-22

Semiconductor device assembly including a chip carrier, semiconductor wafer and method of manufacturing a semiconductor device

 #46
20130037891
2013-02-14

Method of fabricating a semiconductor device having recessed bonding site

 #47
20130023091
2013-01-24

Fused buss for plating features on a semiconductor die

 #48
20120306092
2012-12-06

Conductive pads defined by embedded traces

 #49
20120119367
2012-05-17

Conductive pads defined by embedded traces

 #50
20110024910
2011-02-03

METALLURGY FOR COPPER PLATED WAFERS

 #51
20070111502
2007-05-17

Damascene patterning of barrier layer metal for C4 solder bumps

 #52
20060016861
2006-01-26

Damascene patterning of barrier layer metal for C4 solder bumps