ClassID:

209720

H01L2224/16012 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector; Structure relative to the bonding area, e.g. bond pad

Recent Application in this class:
#1
20260060104
2026-02-26

SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYERS FORMED ON AN ACTIVE WAFER AND METHODS OF MAKING THE SAME

#2
20260033396
2026-01-29

SEMICONDUCTOR PACKAGE INCLUDING CONNECTION TERMINALS

#3
20240389363
2024-11-21

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

#4
20240347493
2024-10-17

SEMICONDUCTOR PACKAGE AND CHIP THEREOF

#5
20240312942
2024-09-19

REFLECTIVE INORGANIC THIN FILM FOR HIGH-DENSITY PANEL-SCALE RE-DISTRIBUTION LAYER (RDL)

#6
20240128209
2024-04-18

Efficient Integration of a First Substrate without Solder Bumps with a Second Substrate Having Solder Bumps

#7
20230307374
2023-09-28

SEMICONDUCTOR DEVICE HAVING REDISTRIBUTION LAYERS FORMED ON AN ACTIVE WAFER AND METHODS OF MAKING THE SAME

#8
20230230946
2023-07-20

SEMICONDUCTOR PACKAGE

#9
20220415813
2022-12-29

INTEGRATED PASSIVE DEVICE DIES AND METHODS OF FORMING AND PLACEMENT OF THE SAME

#10
20200402958
2020-12-24

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

#11
20200161272
2020-05-21

Lead-free solder joining of electronic structures

#12
20200075464
2020-03-05

Chip attached to a die pad having a concave structure

#13
20190252347
2019-08-15

Trace Design for Bump-on-Trace (BOT) Assembly

#14
20190221446
2019-07-18

Semiconductor package structure and method for manufacturing the same

#15
20190081018
2019-03-14

Method for preparing a semiconductor package

#16
20190006312
2019-01-03

Lead-free solder joining of electronic structures

#17
20180337154
2018-11-22

Combing bump structure and manufacturing method thereof

#18
20180190607
2018-07-05

Semiconductor package and method for preparing the same

#19
20170323863
2017-11-09

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

#20
20170207190
2017-07-20

Connection body and method of manufacturing connection body

#21
20170186723
2017-06-29

Trace design for bump-on-trace (BOT) assembly

#22
20160372437
2016-12-22

SEMICONDUCTOR PACKAGE

#23
20160343680
2016-11-24

Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

#24
20160336287
2016-11-17

Semiconductor substrate and semiconductor package structure having the same

#25
20160240501
2016-08-18

Reduced volume interconnect for three-dimensional chip stack

#26
20160211242
2016-07-21

Reduced volume interconnect for three-dimensional chip stack

#27
20160211236
2016-07-21

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

#28
20150333030
2015-11-19

Bonding wire to bonding pad

#29
20150187719
2015-07-02

Trace Design for Bump-on-Trace (BOT) Assembly

#30
20140252652
2014-09-11

Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package

#31
20120139126
2012-06-07

Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package

#32
20100224993
2010-09-09

Forming sacrificial composite materials for package-on-package architectures and structures formed thereby

#33
15592181
2018-09-04

Combing bump structure and manufacturing method thereof

#34
15493096
2018-02-13

Multi-chip semiconductor package, vertically-stacked devices and manufacturing thereof