210878 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding; Bonding techniques Soldering or alloying
Sub-classes:PROCEDURE TO ENABLE DIE REWORK FOR HYBRID BONDING
#2POWER MODULE WITH BALANCED CURRENT FLOW
#3PACKAGE SUBSTRATE HAVING EMBEDDED ELECTRONIC COMPONENT MOUNTED ON CORE OF THE PACKAGE SUBSTRATE
#4DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE
#5DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
#6Display device and method for fabricating the same
#7A PROCEDURE TO ENABLE DIE REWORK FOR HYBRID BONDING
#8Display device and method for fabricating the same
#9Display device having pixels with the same active layer and method thereof
#10DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
#11APPARATUS FOR TRANSFERRING ELECTRONIC COMPONENT, METHOD FOR TRANSFERRING ELECTRONIC COMPONENT AND MANUFACTURING METHOD OF LIGHT-EMITTING DIODE PANEL
#12Semiconductor package with low parasitic connection to passive device
#13Method of fabricating a semiconductor package
#14Method of manufacturing semiconductor element, and semiconductor element body
#15Display device and method of manufacturing the display device
#16Method of manufacturing semiconductor package structure
#17Bond pads for low temperature hybrid bonding
#18Multi-chip package with offset 3D structure
#19Method of manufacturing semiconductor package structure
#20Semiconductor package and method of fabricating a semiconductor package
#21Serializer-deserializer die for high speed signal interconnect
#22Bond pads for low temperature hybrid bonding
#23Multi-chip package with offset 3D structure
#24Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost Package
#25Method for manufacturing chip cards and chip card obtained by said method
#26Method of manufacturing semiconductor device and semiconductor device
#27Method of manufacturing semiconductor package structure
#283D Compute circuit with high density z-axis interconnects
#29ROOM TEMPERATURE METAL DIRECT BONDING
#30Semiconductor apparatus and method for preparing the same
#31Electronic module with sealing resin
#32Method for preparing a semiconductor apparatus
#33SUBSTRATE ATTACHMENT FOR ATTACHING A SUBSTRATE THERETO
#34Copper structures with intermetallic coating for integrated circuit chips
#35Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure
#36Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure
#37Semiconductor-on-insulator with back side heat dissipation
#38Method for bonding substrates
#39Copper structures with intermetallic coating for integrated circuit chips
#40Semiconductor device, metal member, and method of manufacturing semiconductor device
#41Semiconductor structure and fabrication method thereof
#42Room temperature metal direct bonding
#43Semiconductor laser structure
#44SOLDER-CONTAINING SEMICONDUCTOR DEVICE, MOUNTED SOLDER-CONTAINING SEMICONDUCTOR DEVICE, PRODUCING METHOD AND MOUNTING METHOD OF SOLDER-CONTAINING SEMICONDUCTOR DEVICE
#45Semiconductor device and method for manufacturing a semiconductor device
#46SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#47Semiconductor-on-insulator with back side strain topology
#48Optical coupling module
#49Substrate, method of fabricating the same, and application the same
#50Method for manufacturing semiconductor device and semiconductor device
#51Room temperature metal direct bonding
#52Transistor formation using cold welding
#53Transistor formation using cold welding
#54Integrated circuit, a chip package and a method for manufacturing an integrated circuit
#55Method for thin die-to-wafer bonding
#56Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging
#57Semiconductor-on-insulator with back side strain inducing material
#58Room temperature metal direct bonding
#59Semiconductor-on-insulator with back side heat dissipation
#603D integration structure and method using bonded metal planes
#61Semiconductor package, module, system having solder ball coupled to chip pad and manufacturing method thereof
#62Room temperature metal direct bonding
#63Room temperature metal direct bonding