211137 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] Forming a build-up interconnect
Sub-classes:3DIC Interconnect Apparatus and Method
#2Interconnect Layout for Semiconductor Device
#3SEMICONDUCTOR PACKAGE STRUCTURE
#4Semiconductor Device and Method of Integrating eWLB with E-bar Structures and RF Antenna Interposer
#5FAN-OUT PACKAGE STRUCTURE AND FABRICATION METHOD THEREFOR
#6MULTI-CHIP INTERCONNECTION PACKAGE STRUCTURE WITH HEAT DISSIPATION PLATE AND PREPARATION METHOD THEREOF
#7Interconnect Layout for Semiconductor Device
#8MULTI-CHIP INTERCONNECTION PACKAGE STRUCTURE WITH HEAT DISSIPATION PLATE AND PREPARATION METHOD THEREOF
#9PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
#10PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
#11PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN AN INTEGRATED DEVICE AND A METALLIZATION PORTION
#12Semiconductor package structure comprising via structure and redistribution layer structure
#13FIRST CHIP AND WAFER BONDING METHOD AND CHIP STACKING STRUCTURE
#14MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER
#15Display with embedded pixel driver chips
#163DIC Interconnect Apparatus and Method
#17Package structure
#18Semiconductor package structure comprising via structure and redistribution layer structure and method for forming the same
#19MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER
#20Raised via for terminal connections on different planes
#21Interconnect layout for semiconductor device
#22Manufacturing method of semiconductor structure
#23Substrate comprising a high-density interconnect portion embedded in a core layer
#24Package structure and method of manufacturing the same
#25Package structure
#26Display with embedded pixel driver chips
#27SYSTEMS AND METHODS FOR FLASH STACKING
#28Semiconductor package with protected sidewall and method of forming the same
#29Stacked chip package and methods of manufacture thereof
#30Interconnect layout for semiconductor device
#31LED display and electronic device having same
#32Semiconductor device with through silicon via structure
#33Package structure
#34Display with embedded pixel driver chips
#35Semiconductor structure
#36Raised via for terminal connections on different planes
#37Systems and methods for flash stacking
#38Package structure and method of manufacturing the same
#39Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
#40Semiconductor device for bonding conductive layers exposed from surfaces of respective interconnection layers
#41Multi-chip modules formed using wafer-level processing of a reconstituted wafer
#42Semiconductor structure and method of forming
#43Lithography process for semiconductor packaging and structures resulting therefrom
#44Mutli-chip package with encapsulated conductor via
#45Method for manufacturing semiconductor device with through silicon via structure
#463D stacked-chip package
#47LED display and electronic device having same
#48Raised via for terminal connections on different planes
#49Semiconductor package with protected sidewall and method of forming the same
#50Semiconductor structure
#51Semiconductor structure and method of forming
#52Stacked chip package and methods of manufacture thereof
#53Multi-chip modules formed using wafer-level processing of a reconstituted wafer
#543D Chip-on-wager-on-substrate structure with via last process
#55Method of manufacturing semiconductor device and semiconductor device
#56Dual-sided integrated fan-out package
#573DIC interconnect apparatus and method
#58Methods of forming joint structures for surface mount packages
#59Display with embedded pixel driver chips
#60Recessed and embedded die coreless package
#61Fan-out semiconductor package
#62Semiconductor device with through silicon via structure and method for manufacturing the same
#63Embedded die package multichip module
#643DIC interconnect apparatus and method
#65Multi-chip modules formed using wafer-level processing of a reconstitute wafer
#66Electronic module and method for producing same
#67Releasable carrier method
#68Method for integrating at least one 3D interconnection for the manufacture of an integrated circuit
#69Raised via for terminal connections on different planes
#70Method of packaging chip and chip package structure
#71Method for electrically contacting a component by galvanic connection of an open-pored contact piece, and corresponding component module
#72Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
#73Semiconductor device and method
#74Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby
#75RECESSED AND EMBEDDED DIE CORELESS PACKAGE
#763DIC interconnect apparatus and method
#773D chip-on-wafer-on-substrate structure with via last process
#783D stacked-chip package
#79Dual-sided integrated fan-out package
#80Semiconductor device and method
#81Recessed and embedded die coreless package
#82Integrated circuit package
#83Semiconductor device and method
#84Semiconductor device and method
#85Releasable carrier and method
#86Embedded die-down package-on-package device
#87Light emitting device
#883DIC interconnect apparatus and method
#89Embedded electronic packaging and associated methods
#90Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP
#91Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
#92Embedded structures for package-on-package architecture
#93Integrated semiconductor device and wafer level method of fabricating the same
#94Laser assisted transfer welding process
#95BUMPLESS BUILD-UP LAYER PACKAGE INCLUDING A RELEASE LAYER
#96Fan out package structure and methods of forming
#97Recessed and embedded die coreless package
#98Light emitting device
#99Integrated circuit package
#100Method of packaging a semiconductor device
#1013DIC interconnect apparatus and method
#102BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility
#103Method for manufacturing semiconductor device having a multilayer interconnection
#104Microelectronic structures having laminated or embedded glass routing structures for high density packaging
#105Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
#106Integrated semiconductor device and wafer level method of fabricating the same
#107Integrated circuit device packages and methods for manufacturing integrated circuit device packages
#108Embedded electronic packaging and associated methods
#109Semiconductor package with embedded die and its methods of fabrication
#110Method and apparatus for stacked semiconductor chips
#111Embedded structures for package-on-package architecture
#112Semiconductor device with pre-molding chip bonding
#113Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP
#114Recessed and embedded die coreless package
#115Connecting element for a multi-chip module and multi-chip module
#116Integration of laminate MEMS in BBUL coreless package
#117Stacked packaging using reconstituted wafers
#118Method for electrically connecting wafers using butting contact structure and semiconductor device fabricated through the same
#119Die seal ring for integrated circuit system with stacked device wafers
#120Embedded structures for package-on-package architecture
#121Microelectronic structures having laminated or embedded glass routing structures for high density packaging
#122Semiconductor device having wire studs as vertical interconnect in FO-WLP
#123Semiconductor device with pre-molding chip bonding
#124PREVENTION OF THRU-SUBSTRATE VIA PISTONING USING HIGHLY DOPED COPPER ALLOY SEED LAYER
#125Chip package and a method for manufacturing a chip package
#126Thermally enhanced interconnect substrate with embedded semiconductor device and built-in stopper and method of making the same
#127Integrated semiconductor device and wafer level method of fabricating the same
#128Reconstituted wafer-level package DRAM
#129Multi-chip package and method of manufacturing the same
#130Stacked fan-out semiconductor chip
#131Microelectronic assembly tolerant to misplacement of microelectronic elements therein
#132Packaging structure
#133Wiring substrate and method for manufacturing wiring subtrate
#134Method for creating a 3D stacked multichip module
#1353-D Integrated Circuits and Methods of Forming Thereof
#136Combination for composite layered chip package
#137Circuit module with multiple submodules
#138Packaged semiconductor device with a molding compound and a method of forming the same
#139Stacked Packaging Using Reconstituted Wafers
#140Electrically bonded arrays of transfer printed active components
#141Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
#142Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
#143Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die
#144Semiconductor device and fabrication method therefor
#145Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding
#146IMAGE SENSOR UNITS WITH STACKED IMAGE SENSORS AND IMAGE PROCESSORS
#147Multichip Packages
#148Pad bonding employing a self-aligned plated liner for adhesion enhancement
#149Method of fabricating a TSV for 3D packaging of semiconductor device
#1503D integrated circuits structure
#151Laser assisted transfer welding process
#152CHIP PACKAGE STRUCTURE AND MANUFACTURING METHODS THEREOF
#153Package unit and stacking structure thereof
#154Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
#155Chip assembly having via interconnects joined by plating
#156Layered chip package and method of manufacturing same
#157Layered chip package and method of manufacturing same
#158Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
#159Semiconductor apparatus, method of manufacturing semiconductor apparatus, method of designing semiconductor apparatus, and electronic apparatus
#160Semiconductor package with embedded die and its methods of fabrication
#161Method of manufacturing layered chip package
#162Method of manufacturing layered chip package
#163Recessed and embedded die coreless package
#164Three-dimensional integrated circuits and techniques for fabrication thereof
#165Image sensors and methods of manufacturing image sensors
#166Pad bonding employing a self-aligned plated liner for adhesion enhancement
#167Chip package and fabrication method thereof
#168Stacked semiconductor package and method for manufacturing the same
#169Chip package structure and manufacturing methods thereof
#170Microelectronic packages fabricated at the wafer level and methods therefor
#171Method of fabricating a semiconductor device
#172Method of making 3D integrated circuits
#173Lock and key through-via method for wafer level 3 D integration and structures produced
#174Compact multi-port cam cell implemented in 3D vertical integration
#175Three-dimensional integrated circuits and techniques for fabrication thereof
#176Process for fabricating a high-integration-density image sensor
#177Manufacturing method of semiconductor device
#178Stacked semiconductor package and method for manufacturing the same
#179Compact multi-port CAM cell implemented in 3D vertical integration
#180Three dimensional device integration method and integrated device
#181Microelectronic packages fabricated at the wafer level and methods therefor
#182Three dimensional device integration method and integrated device
#183Three dimensional device integration method and integrated device
#184Three dimensional device integration method and integrated device
#185Semiconductor device and method for fabricating the same
#186Package module for an IC device and method of forming the same