ClassID:

211837

H01L2224/92127 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups  - ; Specific sequence of method steps; Connecting a surface with connectors of different types; Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a wire connector

Recent Application in this class:
#1
20250279394
2025-09-04

BRIDGE CHIP, FAN-OUT PACKAGE STRUCTURE AND CORRESPONDING PACKAGING METHOD

#2
20240395763
2024-11-28

SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICE

#3
20240395762
2024-11-28

SEMICONDUCTOR STRUCTURE AND METHOD FOR ARRANGING REDISTRIBUTION LAYER OF SEMICONDUCTOR DEVICE

#4
20230133322
2023-05-04

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

#5
20220285335
2022-09-08

Methods of manufacturing light-emitting devices with metal inlays and bottom contacts

#6
20210249574
2021-08-12

Light-emitting device with metal inlay and bottom contacts

#7
20210249398
2021-08-12

Methods of manufacturing light-emitting devices with metal inlays and bottom contacts

#8
20210249395
2021-08-12

Light-emitting diode lighting system with wirebonded hybridized device

#9
20210118839
2021-04-22

Chip package structure and manufacturing method thereof

#10
20190157197
2019-05-23

Semiconductor device package

#11
20170069603
2017-03-09

Semiconductor devices and packages and methods of forming semiconductor device packages

#12
20160372406
2016-12-22

Electronic device with periphery contact pads surrounding central contact pads

#13
20160111354
2016-04-21

Electronic device with first and second contact pads and related methods

#14
20160035707
2016-02-04

Stacked structure of semiconductor chips having via holes and metal bumps

#15
20160035652
2016-02-04

Integrated Circuit Device With Wire Bond Connections

#16
20150333035
2015-11-19

Articles including bonded metal structures and methods of preparing the same

#17
20150108663
2015-04-23

Semiconductor package and method of fabricating the same

#18
20140342476
2014-11-20

Land grid array semiconductor device packages

#19
20140204552
2014-07-24

Sensor and method for manufacturing sensor

#20
20140103504
2014-04-17

Semiconductor device

#21
20130242500
2013-09-19

Integrated circuit chip using top post-passivation technology and bottom structure technology

#22
20120139103
2012-06-07

Semiconductor device with stacked power converter

#23
20110298128
2011-12-08

Multi-chip package with pillar connection

#24
20110020982
2011-01-27

Method for bonding of chips on wafers

#25
20100246152
2010-09-30

Integrated circuit chip using top post-passivation technology and bottom structure technology

#26
20100157555
2010-06-24

Electrical assembly

#27
20100155938
2010-06-24

Face-to-face (F2F) hybrid structure for an integrated circuit

#28
20070290376
2007-12-20

Integrated circuit (IC) package stacking and IC packages formed by same

#29
20070235865
2007-10-11

Semiconductor module having discrete components and method for producing the same

#30
20070045818
2007-03-01

Land grid array semiconductor device packages

#31
20050034303
2005-02-17

Process to allow electrical and mechanical connection of an electrical device with a face equipped with contact pads