Semiconductor device

Inverted integrated circuit and method of forming the same

Antenna with graded dielectirc and method of making the same

Semiconductor device having an inter-layer via (ILV), and method of making same

Memory array circuit and method of manufacturing same

Read-only memory circuit

Chemical direct pattern plating method

Microelectronic package with substrate cavity for bridge-attach

Semiconductor device including back side power supply circuit

Semiconductor device with source and drain vias having different sizes

Vertical memory devices

SEMICONDUCTOR PACKAGING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

Package structure, package-on-package structure and manufacturing method thereof

Techniques to inhibit delamination from flowable gap-fill dielectric

Semiconductor device including recessed interconnect structure

Integrated circuit packages having mechanical brace standoffs

Manufacturing method of carrier for semiconductor chip mounting thereon

Semiconductor device

SEMICONDCTOR DEVICE PACKAGE THERMAL CONDUIT

OPTICAL DEVICE, SPECTRAL SENSOR MODULE, IMAGING MODULE, AND METHOD FOR MANUFACTURING OPTICAL DEVICE

Image sensors

Vertical memory devices

Semiconductor memory devices and methods for fabricating the same

Vertical memory devices

Manufacturing method of semiconductor memory device and semiconductor memory device

Semiconductor device having vertical fence structures

Method for fabricating semiconductor device

3D NAND memory device and method of forming the same

Semiconductor device with metal plug having rounded top surface

Semiconductor device and method for manufacturing the semiconductor device

Via connection to wiring in a semiconductor device

Methods of forming interconnect structures of semiconductor device

Metal-insulator-metal structure

Semiconductor storage device

Front-end-of-line (FEOL) through semiconductor-on-substrate via (TSV)

Structure and method for interconnection with self-alignment

CuSn via metallization in electrical devices for low-temperature 3D-integration

Staircase formation in three-dimensional memory device

Via-first process for connecting a contact and a gate electrode

Semiconductor device and method for fabricating the same

Embedded device and method of manufacturing the same

Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material

3D semiconductor device and structure

Offset pads over TSV

Semiconductor having a backside wafer cavity for radio frequency (RF) passive device integration and/or improved cooling and process of implementing the same

Strapped copper interconnect for improved electromigration reliability

Barrier removal for conductor in top via integration scheme

Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Microelectronic devices with symmetrically distributed staircase stadiums and related systems and methods

Structure and method of forming a semiconductor device with resistive elements

Interconnect level with high resistance layer and method of forming the same

Semiconductor device and method of fabricating the same

Nitrogen plasma treatment for improving interface between etch stop layer and copper interconnect

Semiconductor device with composite passivation structure and method for preparing the same

Polishing interconnect structures in semiconductor devices

SUPPORTING SUBSTRATE, SUPPORTING SUBSTRATE-ATTACHED LAMINATE AND METHOD FOR MANUFACTURING A PACKAGE SUBSTRATE FOR MOUNTING A SEMICONDUCTOR DEVICE

Resistive random-access memory cell and associated cell array structure

Trench contact structures for advanced integrated circuit structure fabrication

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Vertical memory device and method for fabricating the same

SEMICONDUCTOR STORAGE DEVICE

One time programmable non-volatile memory cell on glass substrate

3D stacked integrated circuits having functional blocks configured to provide redundancy sites

Semiconductor arrangement and method of making

Semiconductor device structure with air gap for reducing capacitive coupling

Process for forming metal-insulator-metal structures

High performance metal insulator metal capacitor

E-fuse co-processed with MIM capacitor

Semiconductor device

Process to yield ultra-large integrated circuits and associated integrated circuits

Fully self-aligned via with selective bilayer dielectric regrowth

Conductive interconnects and methods of forming conductive interconnects

Stepped top via for via resistance reduction

Semiconductor device structure with resistive elements

Multiply accumulate circuit for binary neural network system

INTEGRATED CIRCUIT STRUCTURE

Three-dimensional semiconductor memory device

Three-dimensional semiconductor memory devices

Semiconductor devices

Semiconductor memory device and manufacturing method thereof

Three-dimensional semiconductor device having a first main separation structure and a second main separation structure on a lower structure

Semiconductor device having buried logic conductor type of complementary field effect transistor, method of generating layout diagram and system for same

Semiconductor assembly and method of manufacturing the same

Semiconductor device and method of fabricating the same

Semiconductor device and method of fabricating the same

Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems

Random cut patterning

Semiconductor device having inter-metal dielectric patterns and method for fabricating the same

Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same

Substrate with thermal insulation

Processes for reducing leakage and improving adhesion

Protection structures for bonded wafers

Semiconductor device

Semiconductor structure and method for forming the same

Planarization stop region for use with low pattern density interconnects

Semiconductor device and method of manufacture

Method for fabricating semiconductor interconnect structure and semiconductor structure thereof

Semiconductor device including combination rows and method and system for generating layout diagram of same

Wafer-level packaging of solid-state biosensor, microfluidics, and through-silicon via

Integrated circuits containing vertically-integrated capacitor-avalanche diode structures

Contact over active gate structures for advanced integrated circuit structure fabrication

Interconnect structures of three-dimensional memory devices

Three-dimensional memory device including word line including polysilicon and metal

Three-dimensional memory devices having a backside trench isolation and methods for forming the same

Semiconductor structure

Three-dimensional stacking semiconductor assemblies with near zero bond line thickness

Semiconductor device

Semiconductor device

Liner-free conductive structures with anchor points

Integrated circuit device and method of manufacturing the same

Semiconductor device capable of preventing an increase in the number of manufacturing steps relating to wiring and a method for manufacturing the same

EFuse structure with multiple links

Embedded small via anti-fuse device

SEMICONDUCTOR DEVICE

Semiconductor device with conductors embedded in a substrate

Apparatus with species on or in conductive material on elongate lines

Electron migration control in interconnect structures

Semiconductor device

3D-NAND memory cell structure

Memory cell stack and via formation for a memory device

Three-dimensional semiconductor memory device and method of fabricating the same

Memory device

Interconnect structures of three-dimensional memory devices

Semiconductor storage device with contact melting prevention

Three-dimensional memory device having multi-deck structure and methods for forming the same

Hyperchip

Semiconductor structure and method of fabricating the same

Footing flare pedestal structure

Method and structure to reduce cell width in semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device and method of manufacture

Memory devices and methods for forming the same

Interconnect structure and method for manufacturing the interconnect structure

Conductive lines with subtractive cuts

Fully-aligned skip-vias

Removal or reduction of chamfer for fully-aligned via

Semiconductor memory device and manufacturing method thereof

Integrated circuit package and method

Self-aligned interconnect with protection layer

Barrier-less prefilled via formation

Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication and structures resulting therefrom

Structure and formation method of semiconductor device with stacked conductive structures

Interconnects with spacer structure for forming air-gaps

Methods of manufacturing a semiconductor package

3D semiconductor device and structure

Gate line plug structures for advanced integrated circuit structure fabrication

Semiconductor devices and methods of fabricating the same

Memory device using an etch stop dielectric layer and methods for forming the same

Three-dimensional flash memory device supporting bulk erase operation and manufacturing method therefor

Semiconductor memory device and manufacturing method of the semiconductor memory device

Three-dimensional semiconductor memory device

Three-dimensional semiconductor memory device

Semiconductor memory device and method for manufacturing the same

Semiconductor structure

Integrated circuit and method of generating integrated circuit layout

Memory array circuit and method of manufacturing same

Device for generating security key and manufacturing method thereof

Semiconductor device and forming method thereof

Hybrid conductor integration in power rail

Interconnects with hybrid metal conductors

Top via stack

Memory arrays and methods used in forming a memory array

Top via interconnect with self-aligned barrier layer

Top via with damascene line and via

Deposition system and method using the same

Passivation layer for integrated circuit structure and forming the same

Semiconductor structure and method for fabricating the same

Fin-based strap cell structure

Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays

THREE-DIMENSIONAL MEMORY DEVICE WITH VIA STRUCTURES SURROUNDED BY PERFORATED DIELECTRIC MOAT STRUCTURE AND METHODS OF MAKING THE SAME

THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC ISOLATED VIA STRUCTURES AND METHODS OF MAKING THE SAME

Chip package and manufacturing method thereof

Chip package including substrate inclined sidewall and redistribution line

Semiconductor memory device

Flip-chip semiconductor-on-insulator transistor layout

Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same

Semiconductor package

Semiconductor memory device and method of manufacturing the same

Semiconductor device and manufacturing method of semiconductor device

Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same

Semiconductor package structure and method for manufacturing the same

Semiconductor-on-insulator transistor layout for radio frequency power amplifiers

Gate contact structure over active gate and method to fabricate same

Self-aligned gate contact compatible cross couple contact formation

Method of making a semiconductor structure

Structure and method to improve FAV RIE process margin and Electromigration

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Semiconductor device and method for fabricating the same

Contact structure with insulating cap

Back end of line nanowire power switch transistors

Contact structure and display device including the same

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

Semiconductor device

Vertical type non-volatile memory device and method of manufacturing the same

Memory arrays and methods used in forming a memory array

Memory structure and manufacturing method therefor

Integrated circuit layout, method, structure, and system

Layout structure including anti-fuse cell

INTEGRATED CIRCUIT DEVICE

Three dimensional integrated circuit and fabrication thereof

Layout architecture for a cell

Photonic semiconductor device and method

Package structure

Semiconductor device package and method of manufacturing the same

Semiconductor device and manufacturing method thereof

System on integrated chips and methods of forming the same

Semiconductor device with metal interconnection

Bonding pads embedded in a dielectric diffusion barrier and having recessed metallic liners

Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge

Integrated circuit with non-functional structures

Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication

Skip level vias in metallization layers for integrated circuit devices

Top hat structure for isolation capacitors

Integrated circuits including multi-layer conducting lines

Interconnect device and method

Semiconductor device package and method of manufacturing the same

Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material

Forming self-aligned vias and air-gaps in semiconductor fabrication

Bi-layer alloy liner for interconnect metallization and methods of forming the same

Electrical connection for semiconductor devices

Metal interconnect structure and method for fabricating the same

Mitigating pattern collapse

Semiconductor devices and methods of manufacturing

Integrated circuits having protruding interconnect conductors

Nonvolatile memory device having a vertical structure and a memory system including the same

Semiconductor package and method of fabricating the same

Package structure with solder resist underlayer for warpage control and method of manufacturing the same

Semiconductor devices including shielding layer and methods of manufacturing semiconductor devices

Semiconductor device containing metal-organic framework inter-line insulator structures and methods of manufacturing the same

Methods of forming a conductive contact structure to an embedded memory device on an IC product and a corresponding IC product

3D NAND memory device and method of forming the same

Methods of forming a conductive contact structure to an embedded memory device on an IC product and a corresponding IC product

Conductive contact structures for electrostatic discharge protection in integrated circuits

Memory device including data lines on multiple device levels

Semiconductor assembly with conductive frame for I/O standoff and thermal dissipation

Selective deposition of a protective layer to reduce interconnect structure critical dimensions

Method for making self-aligned barrier for metal vias In-Situ during a metal halide pre-clean and associated interconnect structure

SEMICONDUCTOR DEVICES

Variable resistance memory devices

Three-dimensional memory device containing plural work function word lines and methods of forming the same

Strap-cell architecture for embedded memory

Semiconductor device including anti-fuse cell

Memory device and method of manufacturing the same

Semiconductor device, semiconductor package and method of manufacturing the same

Semiconductor device having interconnection lines with different linewidths and metal patterns

Semiconductor devices

Three-dimensional semiconductor memory device

Integrated circuits including via array and methods of manufacturing the same

Redistribution substrate, method of fabricating the same, and semiconductor package including the same

Self-aligned contacts in three-dimensional memory devices and methods for forming the same

Package structure and method of forming the same

Method of forming a thermal shield in a monolithic 3-d integrated circuit

Semiconductor structure and fabrication method thereof

Semiconductor device with reduced via resistance

Method for fabricating a semiconductor device

Hermetic assembly and device including same

Integrated assemblies having one or more modifying substances distributed within semiconductor material, and methods of forming integrated assemblies

Nonvolatile memory device

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Stacked chips comprising interconnects

Semiconductor device including stack structure with flat region

Package structure and method of fabricating the same

Semiconductor device with through-substrate via

ELECTRONIC CONTROL DEVICE

Metal gate structure cutting process

Semiconductor device and method for manufacturing the same

Metal lead, semiconductor device and methods of fabricating the same

Semiconductor device structure with air gap and method for forming the same

Semiconductor memory device and manufacturing method of the semiconductor memory device

Semiconductor device

Cross-point memory array and related fabrication techniques

Three-dimensional memory devices and fabricating methods thereof

Vertical semiconductor device and method for fabricating the same

Three-dimensional memory devices and fabricating methods thereof

Memory cell structure

Metal space centered standard cell architecture to enable higher cell density

Logic drive based on standardized commodity programmable logic semiconductor IC chips

Apparatus including a dielectric material in a central portion of a contact via, and related methods, memory devices and electronic systems

Die interconnect structures having bump field and ground plane

Apparatus and method to increase effective capacitance with layout staples

Semiconductor device

Semiconductor devices including contacts and conductive line interfaces with contacting sidewalls

Wire interconnect structure of integrated circuit

REDISTRIBUTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Semiconductor device and method of manufacturing the same

Method of forming self-aligned via

Contacts and interconnect structures in field-effect transistors

Magnetic memory devices

Three-dimensional memory device containing a dummy memory film isolation structure and method of making thereof

Packaging scheme involving metal-insulator-metal capacitor

Semiconductor device and method of forming the same

Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure

Semiconductor Devices and Methods of Manufacture

Semiconductor structure and manufacturing method thereof

Interconnect structure with air-gaps

Stacked via structure

Interconnection structure and manufacturing method thereof

Three-dimensional memory device containing structures for enhancing gate-induced drain leakage current and methods of forming the same

Semiconductor device package and method for manufacturing the same