Method of forming semiconductor device

2-D interconnections for integrated circuits

Forming array contacts in semiconductor memories

Integrated circuit, system for and method of forming an integrated circuit

Integrated circuit, system for and method of forming an integrated circuit

Method of generating engineering change order (ECO) layout of base cell and computer-readable medium comprising executable instructions for carrying out said method

Stacked capacitor with enhanced capacitance

Manufacturing method for semiconductor device having hole penetrating stack structure

Electromigration resistant semiconductor device

Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit

Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuit

Doric pillar supported maskless airgap structure for capacitance benefit with unlanded via solution

Integrated circuit chip with power delivery network on the backside of the chip

Methods of forming semiconductor device structures including staircase structures

Semiconductor device

Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit

Stress reduction apparatus with an inverted cup-shaped layer

Integrated shielding and decoupling capacitor structure

Through via structure and manufacturing method thereof

Semiconductor devices with via structure and package structures comprising the same

Composite contact plug structure and method of making same

Staircase encapsulation in 3D NAND fabrication

Electromigration Improvement Using Tungsten For Selective Cobalt Deposition On Copper Surfaces

Advanced interconnect with air gap

Adaptive multi-tier power distribution grids for integrated circuits

Semiconductor device and forming method thereof

Semiconductor device and imaging device

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Three-dimensional memory device having a multilevel drain select gate electrode and method of making thereof

Semiconductor structures and methods of forming the same

Interconnect structure with air-gaps

Integrated packaging devices and methods with backside interconnections

Contact-via chain as corrosion detector

Semiconductor structure and method for forming the same

Substrate and method

ENHANCED VIA FILL MATERIAL AND PROCESSING FOR DUAL DAMASCENE INTEGRATION

Interconnect structure including air gap

Transition metal dry etch by atomic layer removal of oxide layers for device fabrication

Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM)

Field effect transistor device with separate source and body contacts and method of producing the device

Semiconductor memory device

Semiconductor memory device

Method of writing to memory circuit using resistive device

Semiconductor device

Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

Memory circuit layout

Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same

Package substrate having a plurality of chips electrically connected by conductive vias and wiring bonding

Chip package and chip packaging method

Semiconductor device

Semiconductor device, manufacturing method thereof, and electronic apparatus

Integrated circuit comprising an antifuse structure and method of realizing

Wiring with external terminal

Semiconductor memory device having pads of varying widths

Method for fully self-aligned via formation using a directed self assembly (DSA) process

Semiconductor device and fabrication method thereof

Structure and method for capping cobalt contacts

ENCAPSULATION OF COBALT METALLIZATION

Method of processing a substrate and a device manufactured by using the method

Skip via structures

Semiconductor devices and methods of manufacturing the same

Semiconductor device, electronic component, and electronic device

Semiconductor device having semiconductor optical waveguide and opposed insulator-filled trench and manufacturing method thereof

Memory cell structure

Semiconductor device and method of manufacture

Bonding pad structure having island portions and method for manufacturing the same

RADIO FREQUENCY (RF) APPARATUS

On-die seal rings

AVD hardmask for damascene patterning

Semiconductor device and semiconductor package including the same

Structure and formation method of semiconductor device structure

Semiconductor device and manufacturing method thereof

Dual liner silicide

Semiconductor device and method of forming the semiconductor device

Semiconductor device having interconnection structure

Structure and method to improve FAV RIE process margin and electromigration

Structure and method to improve FAV RIE process margin and Electromigration

Radio frequency (RF) switch

Semiconductor package

Semiconductor device having a multilayer wiring structure

Semiconductor chip and multi-chip package using thereof and method for manufacturing the same

Skip-vias bypassing a metallization level at minimum pitch

Selective blocking boundary placement for circuit locations requiring electromigration short-length

Method for manufacturing etch stop areas for contacting semiconductor devices

Structure and method to improve FAV RIE process margin and electromigration

BARRIER PLANARIZATION FOR INTERCONNECT METALLIZATION

BARRIER PLANARIZATION FOR INTERCONNECT METALLIZATION

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Deep trench metal-insulator-metal capacitors

Split rail structures located in adjacent metal layers

Manufacturing method of memory device

IC structure including TSV having metal resistant to high temperatures and method of forming same

Display device

Methods for fabricating a semiconductor memory device

Integrated circuit chip reinforced against front side deprocessing attacks

Semiconductor device and method of producing semiconductor device

Methods for reducing dual damascene distortion

COMPOUND RESISTOR STRUCTURE FOR SEMICONDUCTOR DEVICE

Interconnect structures with fully aligned vias

Vertical memory device including common source line structure

SEMICONDUCTOR DEVICE

Electronic module and method for encapsulation thereof

Underfill control structures and method

Methods of fabricating a semiconductor device having a via structure and an interconnection structure

Interconnection structure and manufacturing method thereof

Interlevel connectors in multilevel circuitry, and method for forming the same

Semiconductor device and semiconductor package

Method to reduce resistance for a copper (Cu) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

Methods of forming metallization lines on integrated circuit products and the resulting products

Middle end-of-line strap for standard cell

Self-aligned contacts

Semiconductor device and method of forming the semiconductor device

Method for fluorocarbon film used as middle stop layer for porous low k film

Fluxgate device with low fluxgate noise

Low temperature fabrication of lateral thin film varistor

Method for improving circuit layout for manufacturability

Method for testing inter-layer connections

Vertical MIM capacitor

Integrated circuit device and method for manufacturing same

Semiconductor memory devices

Integrated circuit (IC) devices including cross gate contacts

Backside ground plane for integrated circuit

Semiconductor device

Power grid layout designs for integrated circuits

Hybrid copper structure for advance interconnect usage

Nitridization for semiconductor structures

Contact trench between stacked semiconductor substrates

Backside device contact

Backside device contact

Backside device contact

Semiconductor package assembly

Two-dimensional self-aligned super via integration on self-aligned gate contact

Three-dimensional memory device containing word lines formed by selective tungsten growth on nucleation controlling surfaces and methods of manufacturing the same

Copper interconnect structure with manganese oxide barrier layer

Integrated circuit having a plurality of active layers and method of fabricating the same

Semiconductor memory device and method for driving same

Three-dimensional semiconductor memory device

Semiconductor memory device and method for manufacturing same

Memory devices

Semiconductor device and method for manufacturing same

Cobalt top layer advanced metallization for interconnects

Cobalt top layer advanced metallization for interconnects

Selective surface modification of interconnect structures

Formation of advanced interconnects

Surface nitridation in metal interconnects

Surface nitridation in metal interconnects

Microelectronic conductive routes and methods of making the same

Methods of forming a semiconductor device structure including a stair step structure

Self-aligned spacer for cut-last transistor fabrication

Copper interconnect structure with manganese oxide barrier layer

Semiconductor device manufacture method

Semiconductor device and manufacturing method thereof

Self-aligned airgaps with conductive lines and vias

Electrical interconnect structure for an embedded electronics package

Metal fill optimization for self-aligned double patterning

Metal cap integration by local alloying

Semiconductor structure and associated fabricating method

STACKED TYPE CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Chip mounting structure

Metal alloy capping layers for metallic interconnect structures

Semiconductor devices having interconnection structure

Interconnect structure having subtractive etch feature and damascene feature

Self-Aligned Interconnection Structure and Method

Chip package structure with conductive pillar and a manufacturing method thereof

Semiconductor memory device

Semiconductor package structure and manufacturing method thereof

Integrated circuits including a dummy metal feature and methods of forming the same

Semiconductor device and manufacturing method of the same

Interconnect arrangement with stress-reducing structure and method of fabricating the same

Semiconductor device and method for manufacturing same

Semiconductor devices and methods of manufacture thereof

Package-on-package structure and method

Post-passivation interconnect structure and methods thereof

Through via structure, semiconductor device and manufacturing method thereof

Metal via structure

Electronic device with delamination resistant wiring board

Copper interconnect for improving radio frequency (RF) silicon-on-insulator (SOI) switch field effect transistor (FET) stacks

Board for electronic component package, electronic component package, and method of manufacturing board for electronic component package

Methods and apparatus for scribe seal structures

Closely packed vertical transistors with reduced contact resistance

Memory metal scheme

Fan-out semiconductor package

Chip protected against back-face attacks

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Cobalt first layer advanced metallization for interconnects

Low aspect ratio interconnect

Avoiding gate metal via shorting to source or drain contacts

Interconnect structure and methods thereof

Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects

Semiconductor via structure with lower electrical resistance

Semiconductor device having a Pd-containing adhesion layer

Cobalt first layer advanced metallization for interconnects

Interconnect structure

Semiconductor device

Manufacturing methods to protect ULK materials from damage during etch processing to obtain desired features

Etch stop for airgap protection

Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

Semiconductor device structure

Buffer layer(s) on a stacked structure having a via

Fan-out packages including vertically stacked chips and methods of fabricating the same

Semiconductor chip with anti-reverse engineering function

Formation of advanced interconnects

Nitridized ruthenium layer for formation of cobalt interconnects

Formation of advanced interconnects including set of metal conductor structures in patterned dielectric layer

Nitridized ruthenium layer for formation of cobalt interconnects

Semiconductor package with core substrate having a through hole

LAYER STACKING STRUCTURE, ARRAY SUBSTRATE AND DISPLAY DEVICE

Integrated circuits with Peltier cooling provided by back-end wiring

Method for fabricating semiconductor device

Semiconductor devices

Tungsten gates for non-planar transistors

Semiconductor device

Memory device having vertical structure

BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC DEVICES

Semiconductor device having a large area interconnect or pad

Semiconductor device

Structure and fabrication method for enhanced mechanical strength crack stop

Interconnection structure and methods of fabrication the same

SEMICONDUCTOR DEVICE

Method of manufacturing semiconductor structure comprising plurality of through holes using metal hard mask

Semiconductor structure and fabrication method thereof

Semiconductor device including contact structure

Formation of a transition metal nitride

Semiconductor device and manufacturing method thereof

Methods for Multi-Wire Routing and Apparatus Implementing Same

TSV testing method and apparatus

Multi-layer film device and method

Semiconductor device and manufacturing method thereof

Semiconductor structure and method of forming

Multiple driver pin integrated circuit structure

Semiconductor memory device

Semiconductor memory device

Integrated circuit including wire structure, related method and design structure

Devices and methods of forming low resistivity noble metal interconnect

Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions

Three dimensional semiconductor memory device having peripheral circuit under cell structure

Dense redistribution layers in semiconductor packages and methods of forming the same

Methods of forming a through-substrate-via (TSV) and a metallization layer after formation of a semiconductor device

Selective recessing to form a fully aligned via

Structure and method to reduce copper loss during metal cap formation

NANOPORE-BASED DNA SENSING DEVICE WITH NEGATIVE CAPACITANCE FOR IMPROVED DNA SENSING SIGNAL

Pillar-shaped semiconductor memory device and method for producing the same

Fan-out semiconductor package

Method for manufacturing semiconductor structure

Semiconductor device having a dual material redistribution line

Semiconductor device and manufacturing method of semiconductor device

Semiconductor device structure

Semiconductor device and manufacturing method thereof

Programmable via devices with metal/semiconductor via links and fabrication methods thereof

Dual-mode wireless charging device

Semiconductor devices including electrically isolated patterns and method of fabricating the same

Interconnect structure having power rail structure and related method

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Method and structure of forming low resistance interconnects

Formation method of interconnection structure of semiconductor device

Method for forming conductive structure in semiconductor structure

Reducing contact resistance in vias for copper interconnects

Electronic device

Heterojunction semiconductor device having source and drain pads with improved current crowding

Semiconductor device and method of manufacturing the semiconductor device

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semicondcutor structure and semiconductor manufacturing process thereof

Semiconductor device and a method of manufacturing the same

Prevention of premature breakdown of interline porous dielectrics in an integrated circuit

Semiconductor device having structure for improving voltage drop and device including the same

Interconnection structure and method of forming the same

Metal cap integration by local alloying

Semiconductor device and method

Aligning conductive vias with trenches

Method of forming trenches with different depths

Manufacturing method of semiconductor device and semiconductor device

Method and structure for dual sheet resistance trimmable thin film resistors at same level

Selective tungsten growth for word lines of a three-dimensional memory device

Electronic device

Calibration kits for RF passive devices

Antenna on integrated circuit package

Dual power structure with connection pins

Semiconductor device and method for fabricating the same

Semiconductor devices and methods for forming a semiconductor device

Multi-level air gap formation in dual-damascene structure

Multi-level air gap formation in dual-damascene structure

Multi-level air gap formation in dual-damascene structure

AMORPHOUS CARBON LAYER FOR COBALT ETCH PROTECTION IN DUAL DAMASCENE BACK END OF THE LINE INTEGRATED CIRCUIT METALLIZATION INTEGRATION

Semiconductor device having inductor

Method and apparatus for placing a gate contact inside an active region of a semiconductor

Hybrid interconnects and method of forming the same

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Systems and methods to enhance passivation integrity

Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps

Method for reducing via RC delay

Interconnect structure formed with a high aspect ratio single damascene copper line on a non-damascene via

Design-aware pattern density control in directed self-assembly graphoepitaxy process

INTERCONNECTS WITH INNER SACRIFICIAL SPACERS

Semiconductor device and method of manufacturing the same

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

Integrated circuit package stack

Methods of forming multi-die package structures including redistribution layers