Cavity generation for embedded interconnect bridges utilizing temporary structures

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Semiconductor package and manufacturing method of the same

Techniques to improve reliability in Cu interconnects using Cu intermetallics

Memory cell and array structure having a plurality of bit lines

Enhanced self-alignment of vias for asemiconductor device

Wafer level chip scale package structure and manufacturing method thereof

Semiconductor device including dual trench epitaxial dual-liner contacts

Semiconductor contact

Methods of enhancing polymer adhesion to copper

Barrier layers in trenches and vias

Semiconductor interconnect structure and manufacturing method thereof

Etch stop layer for semiconductor devices

Self-aligned pattern formation for a semiconductor device

Via cleaning to reduce resistance

Self-aligned airgaps with conductive lines and vias

Method, apparatus and system for wide metal line for SADP routing

Semiconductor device including a LDMOS transistor and method

MEMORY DEVICE HAVING VERTICAL STRUCTURE

Inter-plane offset in backside contact via structures for a three-dimensional memory device

Semiconductor device

Vertical metal insulator metal capacitor having a high-k dielectric material

Semiconductor switch device

Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages

Semiconductor package and manufacturing method of the same

Semiconductor chip and multi-chip package using thereof

INTERCONNECTS HAVING HYBRID METALLIZATION

Conductive terminal on integrated circuit

Thermally conductive and electrically isolating layers in semiconductor structures

Gate tie-down enablement with inner spacer

Self-aligned contact

Self-aligned contact

Substrate and method including forming a via comprising a conductive liner layer and conductive plug having different microstructures

Interconnect structure and method

Conformal low temperature hermetic dielectric diffusion barriers

Semiconductor chip including region having rectangular-shaped gate structures and first metal structures

Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures

Vertical non-volatile memory device and method for fabricating the same

Vertical memory devices and methods of manufacturing the same

Using inter-tier vias in integrated circuits

Semiconductor device and method of fabricating the same

Fan-out semiconductor package

Method of producing a semiconductor device with through-substrate via covered by a solder ball

Copper interconnect structures

Semiconductor device and manufacturing method thereof

Via patterning using multiple photo multiple etch

Semiconductor device and communication circuit

Semiconductor device and method for manufacturing semiconductor device

Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures

Method of forming a staircase in a semiconductor device using a linear alignment control feature

Within-array through-memory-level via structures and method of making thereof

Systems and methods for a sequential spacer scheme

Package substrate having noncircular interconnects

Semiconductor Device and Method of Fabricating the Same

Metal-graphene heterojunction metal interconnects, method of forming the same, and semiconductor device including the same

Semiconductor structure

Multi-barrier deposition for air gap formation

Methods and devices for reducing program disturb in non-volatile memory cell arrays

Semiconductor device and method of manufacturing the same

Semiconductor device and manufacturing method thereof

Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method of making the same

Integrated circuit and standard cell library

Connector formation methods and packaged semiconductor devices

Integrated circuit having staggered conductive features

Semiconductor device and manufacturing method thereof

Avoiding gate metal via shorting to source or drain contacts

Assemblies having shield lines of an upper wiring level electrically coupled with shield lines of a lower wiring level

Low resistance dual liner contacts for fin field-effect transistors (FinFETs)

Method for producing self-aligned line end vias and related device

Interconnect structures with enhanced electromigration resistance

Interconnect structures with enhanced electromigration resistance

Hardmask layer for 3D NAND staircase structure in semiconductor applications

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Semiconductor device and method of manufacturing the same

Vertical memory devices

Semiconductor device and manufacturing method thereof

Semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

PACKAGE INCLUDING STACKED DIE AND PASSIVE COMPONENT

DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT WITH IMPROVED ADHESION

Contact structure and formation thereof

Electrical fuse structure and method of formation

Integrated circuit having slot via and method of forming the same

Devices and methods of forming low resistivity noble metal interconnect

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor device and semiconductor package

Semiconductor devices and methods for forming a semiconductor device

Method of forming pattern of semiconductor device

Reducing neighboring word line in interference using low-k oxide

Multi-layer integrated circuits having isolation cells for layer testing and related methods

Adaptive capacitors with reduced variation in value and in-line methods for making same

Three-dimensional semiconductor device

Semiconductor device and method for manufacturing the same

Semiconductor device and method of manufacture

Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

METHOD OF MAKING VERTICAL AND BOTTOM BIAS E-FUSES AND RELATED DEVICES

Method of forming interconnect structures by self-aligned approach

Semiconductor device and fabricating method thereof

Acoustic wave device

Semiconductor device including via plugs

Three-dimensional semiconductor memory devices

Semiconductor device

Manufacturing method of a semiconductor device and semiconductor device

Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same

Air gap over transistor gate and related method

Trench silicide with self-aligned contact vias

Electronic component package and method of manufacturing the same

Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme

Semiconductor structure and testing method using the same

SGT-including pillar-shaped semiconductor device and method for producing the same

METHOD, APPARATUS, AND SYSTEM FOR IMPROVED CELL DESIGN HAVING UNIDIRECTIONAL METAL LAYOUT ARCHITECTURE

VERTICAL MEMORY DEVICES

Semiconductor memory device including 3-dimensional structure and method for manufacturing the same

Semiconductor devices having staggered air gaps

Gas-Cooled 3D IC with Wireless Interconnects

Integrated circuit package having pin up interconnect

Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance

Metal landing method for RRAM technology

Methods of forming integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material

Static random access memory (SRAM) cell including fin-type transistor

Oversized Contacts and Vias in Layout Defined by Linearly Constrained Topology

Integrated circuit, system for and method of forming an integrated circuit

Wafer bonding edge protection using double patterning with edge exposure

Semiconductor device, semiconductor chip and method of manufacturing the semiconductor device

Composite manganese nitride / low-k dielectric cap

Selective and non-selective barrier layer wet removal

Method of manufacturing self-aligned interconnects by deposition of a non-conformal air-gap forming layer having an undulated upper surface

Ruthenium metal feature fill for interconnects

Through substrate vias with improved connections

Method for forming interconnect structure of semiconductor device

Structure and formation method of damascene structure

Enhancement of iso-via reliability

Fluxgate device with low fluxgate noise

Light-erasable embedded memory device and method of manufacturing the same

Integrated circuit and layout method

Side bottom contact RRAM structure

Manufacturing method of memory device

Pillar-shaped semiconductor memory device and method for producing the same

Semiconductor device and method of manufacturing the same

Semiconductor device including stacked die with continuous integral via holes

Semiconductor Devices with On-Chip Antennas and Manufacturing Thereof

Interconnect structure having tungsten contact copper wiring

Metal-insulator-metal capacitor and methods of fabrication

Semiconductor device and layout design thereof

Devices and methods for forming cross coupled contacts

Electronic component package and method of manufacturing the same

Interconnect structure with porous low k dielectric and barrier layer

Metal interconnect structure

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Nonvolatile memory device and method for fabricating the same

Erasable programmable non-volatile memory

Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

Semiconductor device and design method of same

Semiconductor device

Electrostatic discharge protection for antenna using vias

Semiconductor apparatus with fake functionality

Vertical interconnects for self shielded system in package (SiP) modules

Line structure and a method for producing the same

Selective and non-selective barrier layer wet removal

Airgap protection layer for via alignment

STRUCTURE AND PROCESS FOR METAL CAP INTEGRATION

Advanced metal connection with metal cut

Method and apparatus for single chamber treatment

Random number generator device and control method thereof

NEUROMORPHIC DEVICE INCLUDING SYNAPSES HAVING FIXED RESISTANCE VALUES

Semiconductor structure

Acoustic wave device

Semiconductor memory device

Semiconductor structure having gate replacement and method for manufacturing the same

Standard cell for removing routing interference between adjacent pins and device including the same

Semiconductor layout structure

Vertical memory devices and methods of manufacturing the same

Semiconductor structure having etching stop layer and manufacturing method of the same

Semiconductor device structures including staircase structures, and related methods and electronic systems

Semiconductor interconnect structure with double conductors

Semiconductor interconnect structure with double conductors

Semiconductor device and method for forming the same

Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure

Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof

Reliable packaging and interconnect structures

Formation of getter layer for memory device

Semiconductor device

Two-dimensional self-aligned super via integration on self-aligned gate contact

Methods for forming 2-dimensional self-aligned vias

Two-dimensional self-aligned super via integration on self-aligned gate contact

Structure and method for interconnection

Semiconductor structure and memory device including the structure

Display having vertical gate line extensions and minimized borders

Magnetically-coupled inductors on integrated passive devices and assemblies including same

Integrated passive devices and assemblies including same

Embedded chip packages and methods for manufacturing an embedded chip package

Socket structure for three-dimensional memory

Semiconductor memory device

Static random access memory (SRAM) device

3D cross-point memory manufacturing process having limited lithography steps

3D cross-point memory manufacturing process having limited lithography steps

SEMICONDUCTOR DIE, SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME

Alignment mark design for packages

Semiconductor device and manufacturing method thereof

Three dimensional storage cell array with highly dense and scalable word line design approach

Localized high density substrate routing

Treating copper interconnects

Methods for manufacturing semiconductor device and for detecting end point of dry etching

Interconnect structure having an etch stop layer over conductive lines

Method for manufacturing semiconductor device with trench isolation structure having plural oxide films

Method of forming a dual metal interconnect structure

Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line

Electronic device with integrated galvanic isolation, and manufacturing method of the same

High aspect ratio contact metallization without seams

Semiconductor devices including a capping layer

Method for layout design and structure with inter-layer vias

Interconnect structure including air gaps enclosed between conductive lines and a permeable dielectric layer

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

Semiconductor device

Interconnect structure for semiconductor devices

Self-aligned gate contact

High performance middle of line interconnects

Method of manufacturing a wiring structure on a self-forming barrier pattern

Method of forming trenches with different depths

Method of manufacturing an interconnect without dielectric exclusion zones by thermal decomposition of a sacrificial filler material

Hybrid carbon-metal interconnect structures

Semiconductor memory device with charge-diffusion-less transistors

Semiconductor device and method for manufacturing the same

Deep trench capacitor with a filled trench and a doped region serving as a capacitor electrode

Dual-layer dielectric in memory device

Semiconductor memory device and method of manufacturing the same

Semiconductor device

Semiconductor device

Vertical memory devices and methods of manufacturing the same

Area-efficient and robust electrostatic discharge circuit

INTEGRATED CIRCUIT, AND DESIGN METHOD, DESIGN APPARATUS AND DESIGN PROGRAM FOR INTEGRATED CIRCUIT

Semiconductor devices for integration with light emitting chips and modules thereof

Oxidation resistant barrier metal process for semiconductor devices

Semiconductor device having a metal adhesion and barrier structure and a method of forming such a semiconductor device

Semiconductor device and wafer level package including such semiconductor device

Semiconductor device and method for manufacturing semiconductor device

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

Semiconductor device including a passive component formed in a redistribution layer

Semiconductor device and a method of manufacturing the same

Semiconductor memory device having a stepped structure and contact wirings formed thereon

Integrated circuit device

Semiconductor device and method

Saw resonator having negative profile metal structure and manufacturing method thereof

Composite and transistor

Semiconductor device, semiconductor wafer, module, electronic device, and manufacturing method the same

SEMICONDUCTOR MEMORY DEVICE

Stacked non-volatile semiconductor memory device with buried source line and method of manufacture

Semiconductor chip with anti-reverse engineering function

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Power and ground routing of integrated circuit devices with improved IR drop and chip performance

Semiconductor device and method for manufacturing same

Conductive structures, systems and devices including conductive structures and related methods

Structure and method to self align via to top and bottom of tight pitch metal interconnect layers

Semiconductor device and designing method thereof

Structure and formation method of semiconductor device structure

Metallic blocking layer for reliable interconnects and contacts

Encapsulated power semiconductor device having a metal moulded body as a first connecting conductor

Semiconductor device

Materials and deposition schemes using photoactive materials for interface chemical control and patterning of predefined structures

Crossbar switch with an arrangement of wires, logic integrated circuit using the same, and semiconductor device

Sharing Capacitor, Pixel Having Sharing Capacitor, And Array Substrate Having Sharing Capacitor

Semiconductor memory devices

Localized redistribution layer structure for embedded component package and method

SEMICONDUCTOR DEVICE

Semiconductor device

Hybrid metal interconnects with a bamboo grain microstructure

E-fuse structure of semiconductor device

Ultra high performance interposer

Semiconductor structure and method making the same

Low capacitance through substrate via structures

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Integrated circuit device having an air gap between interconnects and method for manufacturing the same

Middle end-of-line strap for standard cell

Self-aligned interconnects

Interconnect structure and method

Semiconductor device including an electrically floated dummy contact plug and a method of manufacturing the same

Monolayer thin film capacitor

Semiconductor package assembly

Integrated circuit die having backside passive components and methods associated therewith

Alignment mark design for packages

Methods for microelectronics fabrication and packaging using a magnetic polymer

Systems and methods for microelectronics fabrication and packaging using a magnetic polymer

Low stress vias

Semiconductor device and method of manufacturing the same

Stacked device and associated layout structure

Methods for isolating portions of a loop of pitch-multiplied material and related structures

Via self alignment and shorting improvement with airgap integration capacitance benefit

Compensating for lithographic limitations in fabricating semiconductor interconnect structures

Ultra dense vertical transport FET circuits

Semiconductor memory device and method for manufacturing the same

Semiconductor memory device

Semiconductor memory device and method of manufacturing semiconductor memory device

SEMICONDUCTOR DEVICE

Semiconductor arrangement and formation thereof

Semiconductor device including air gaps between interconnects and method of manufacturing the same

Semiconductor device interconnect structures formed by metal reflow process

Semiconductor structure having tapered damascene aperture and method of the same

Method, apparatus, and system for MOL interconnects without titanium liner