Dielectric with air gaps for use in semiconductor devices

Isolation of circuit elements using front side deep trench etch

Semiconductor device, manufacturing method thereof, and electronic device

Array substrate and display panel with same

Semiconductor memory device

Low resistance contact structures including a copper fill for trench structures

Vertical memory devices and methods of manufacturing the same

Inductor device and method of manufacturing the same

Contact via structure and fabricating method thereof

Semiconductor device and method of manufacturing the same

LOW RESISTANCE CONTACT STRUCTURES INCLUDING A COPPER FILL FOR TRENCH STRUCTURES

Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrier

Self aligned via and pillar cut for at least a self aligned double pitch

Semiconductor devices and methods of manufacturing the same

Magnetoresistive sensor module and method for manufacturing the same

Interconnect apparatus and method

Semiconductor memory device and method for manufacturing the same

Semiconductor die contact structure and method

Dual power structure with connection pins

Conductive structures, systems and devices including conductive structures and related methods

Bonding structures and methods forming the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Interconnection structure and method of forming the same

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Semiconductor device

ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME

Selective bottom-up metal feature filling for interconnects

Nonvolatile memory device and method for fabricating the same

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

LIQUID COMPOSITION FOR CLEANING SEMICONDUCTOR DEVICE, METHOD FOR CLEANING SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Method of forming dielectric with air gaps for use in semiconductor devices

Three-dimensionally integrated circuit devices including oxidation suppression layers

Adaptive capacitors with reduced variation in value and in-line methods for making same

Low temperature fabrication of lateral thin film varistor

Vertical memory devices

Semiconductor device

Forming interlayer dielectric material by spin-on metal oxide deposition

Semiconductor device and manufacturing method thereof

Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the same

Semiconductor device having jumper pattern

Prevention of premature breakdown of interline porous dielectrics in an integrated circuit

Contacts for semiconductor devices and methods of forming thereof

Semiconductor device layout having a power rail

Semiconductor structure with ultra thick metal and manufacturing method thereof

Interconnection structure and manufacturing method thereof

Mask and metal wiring of a semiconductor device formed using the same

Wiring board including multiple wiring layers that are different in surface roughness

Methods of forming an integrated circuit chip having two types of memory cells

Integrated two-terminal device and logic device with compact interconnects having shallow via for embedded application

Flexible LED display

Composite wafer semiconductor devices using offset via arrangements and methods of fabricating the same

Semiconductor device

Semiconductor device and manufacturing method thereof

Multiple pre-clean processes for interconnect fabrication

Integrated circuit devices and methods

Programmable via devices with metal/semiconductor via links and fabrication methods thereof

Semiconductor apparatus, system, and method of manufacturing semiconductor apparatus

Integrated fan-out structure and method of forming

Structure and method for interconnection

Multi-layer full dense mesh

Conductive plug structure and fabrication method thereof

Electrochemical plating

Three-dimensional semiconductor device

Localized redistribution layer structure for embedded component package and method

Compact semiconductor package and related methods

Semiconductor chip with anti-reverse engineering function

Integrated circuit with power saving feature

Electrically conductive interconnect including via having increased contact surface area

Interconnects through dielectric vias

Vertical memory devices and methods of manufacturing the same

Dual liner silicide

Seam healing of metal interconnects

Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

Method of forming metal interconnection

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND RECORDING MEDIUM

Socket structure for three-dimensional memory

Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

Semiconductor device

Segmented power transistor

Contacts for highly scaled transistors

Memory device and method of manufacturing the same

Three dimensional vertical channel semiconductor memory device

Semiconductor memory device

SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE

Semiconductor memory device and method of manufacturing the same

Semiconductor device having supporters and method of manufacturing the same

Monolithic microwave integrated circuits

Via bottom structure and methods of forming

Semiconductor memory device with contact plugs extending inside contact connection portions

Semiconductor memory device

Method for manufacturing an SGT-including semiconductor device

Semiconductor devices having an air gap

Semiconductor pillars charged in read operation

Method of forming body contact layouts for semiconductor structures

Metal thin film resistor and process

Monolithic integration techniques for fabricating photodetectors with transistors on same substrate

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Metal line with increased inter-metal breakdown voltage

Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same

Plasma protection diode for a HEMT device

Air trench in packages incorporating hybrid bonding

SEMICONDUCTOR DEVICE INCLUDING PASSIVE EQUALIZER CIRCUIT

Semiconductor device and manufacturing method thereof

Semiconductor device allowing metal layer routing formed directly under metal pad

Method of preventing pattern collapse

Apparatus and method for placing stressors within an integrated circuit device to manage electromigration failures

Semiconductor device and method of manufacturing the same

CAPACITOR FORMED IN SEMICONDUCTOR

Semiconductor device and electronic apparatus encapsulated in resin with embedded filler particles

Semiconductor chip package and method of manufacturing the same

Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making

Package systems including passive electrical components

SURFACE ENCAPSULATION FOR WAFER BONDING

Integrated circuit with lateral flux capacitor

Three-dimensional semiconductor memory devices

Semiconductor device including three dimensional memory string

Method of making a multilevel memory stack structure using a cavity containing a sacrificial fill material

Metal layers for a three-port bit cell

Semiconductor devices including nanowire capacitors and fabricating methods thereof

Via placement within an integrated circuit

3DIC package and methods of forming the same

POWER CONVERTING DEVICE

Methods of forming multi-die package structures including redistribution layers

Electronic component device

Semiconductor device, method for manufacturing semiconductor device and alignment mark

Semiconductor devices having air spacers and methods of manufacturing the same

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device

Integrated circuit structures comprising conductive vias and methods of forming conductive vias

Methods of forming semiconductor device structures including stair step structures

Chamferless via structures

Three-dimensional semiconductor memory device

Semiconductor device and method of manufacturing the same

Semiconductor device having wire bonding connection and method for manufacturing the same

Semiconductor devices and methods of manufacturing the same

Semiconductor device

Methods for manufacturing semiconductor device and for detecting end point of dry etching

SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS

Chamferless via structures

Semiconductor device manufacturing method and storage medium

High capacity I/O (input/output) cells

3D shaped inductive charging coil and method of making the same

PHOTONIC DEVICES WITH THROUGH DIELECTRIC VIA INTERPOSER

Semiconductor device

Dummy bottom electrode in interconnect to reduce CMP dishing

Antifuse-type one time programming memory cell and array structure with same

Antifuse-type one time programming memory cell and array structure with same

Double-side process silicon MOS and passive devices for RF front-end modules

Three-dimensional integrated circuit structure and bonded structure

Wafer bonding edge protection using double patterning with edge exposure

Trench liner for removing impurities in a non-copper trench

Interconnection structure and methods of fabrication the same

Semiconductor device and method for manufacturing the same

Semiconductor device structure and method for forming the same

Memory device and method of manufacturing the same

Via structure for optimizing signal porosity

Interconnect structure with twin boundaries and method for forming the same

Method of forming metal interconnection

Structure and method for interconnection

PROTON RESISTIVE MEMORY DEVICES AND METHODS

Semiconductor metallization structure

Nonvolatile memory device having pad structure for high speed operation

Semiconductor device having channel holes

Semiconductor device and method of manufacturing the same

Device having an inter-layer via (ILV), and method of making same

Semiconductor device structure and method for forming the same

Stress tuning for reducing wafer warpage

Semiconductor device including fuse structure

Conductive through-polymer vias for capacitative structures integrated with packaged semiconductor chips

Reducing liner corrosion during metallization of semiconductor devices

Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion

FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES

Self-aligned back end of line cut

Semiconductor device having insulating layers containing oxygen and a barrier layer containing manganese

Connector structure and method for fabricating the same

Metal capping process and processing platform thereof

Heterojunction semiconductor device for reducing parasitic capacitance

Semiconductor devices having a pad structure

Semiconductor device having through silicon vias and manufacturing method thereof

Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques

AVD hardmask for damascene patterning

Integrated circuit having slot via and method of forming the same

Semiconductor device including source/drain contact having height below gate stack

Hybrid subtractive etch/metal fill process for fabricating interconnects

HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS

Capacitor in post-passivation structures and methods of forming the same

Semiconductor devices

Self-aligned contacts

Damascene wires with top via structures

Hybrid subtractive etch/metal fill process for fabricating interconnects

Desmear with metalized protective film

Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of imidazole and bisepoxide compounds

Semiconductor device and method of manufacturing the same

Semiconductor device

Multi-device package and manufacturing method thereof

Semiconductor device and a method of manufacturing the same

Interconnection structure

Semiconductor devices

Semiconductor device and method for fabricating the same

Semiconductor device having a porous low-k structure

Semiconductor device having a multi-level interconnection structure

Interconnect arrangement with stress-reducing structure and method of fabricating the same

Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions

Method of manufacturing a semiconductor device having groove-shaped via-hole

Redistribution lines having stacking vias

Varainductor and operation method thereof based on mutual capacitance

Stacked chip layout having overlapped regions

Electrode connecting structure including adhesion layer and electronic device including the same

Conductive line patterning

Hybrid bond using a copper alloy for yield improvement

Conductive seal ring for power bus distribution

SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF

Antifuse structure in via hole in interplayer dielectric

Semiconductor device with through-substrate via covered by a solder ball

Semiconductor memory device and method for manufacturing the same

Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof

METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION

Method for interconnect scheme

Via pattern to reduce crosstalk between differential signal pairs

Network unit of electronic appliances, network of electronic appliances, and method of using chip identification device

Method for forming wiring

SEMICONDUCTOR MEMORY DEVICE

Method of producing a semiconductor device with through-substrate via covered by a solder ball

Microelectronic assemblies formed using metal silicide, and methods of fabrication

Transmission line for 3D integrated circuit

Semiconductor device

Semiconductor device having structure for improving voltage drop and device including the same

VIA STRUCTURES FOR THERMAL DISSIPATION

Method of semiconductor integrated circuit fabrication

Interconnect structure for semiconductor devices

Layered benzocyclobutene interconnected circuit and method of manufacturing same

Integrated biosensor

Trench MOSFET with depleted gate shield and method of manufacture

Semiconductor memory device

Semiconductor memory device and method for manufacturing the same

Semiconductor device and method of producing semiconductor device

SELF-ALIGNED BARRIER AND CAPPING LAYERS FOR INTERCONNECTS

Semiconductor integrated circuit and electronic system including the same

Semiconductor interconnect structures

Thickened stress relief and power distribution layer

Semiconductor device having interconnection structure

Semiconductor device and manufacturing method thereof

Insulated die

Conductive plug and method of forming the same

Connectible nanotube circuit

Semiconductor structures including carrier wafers and attached device wafers, and methods of forming such semiconductor structures

Semiconductor switch

Semiconductor device including dummy metal

Semiconductor device having air gap spacer and method of fabricating the same

Distributed decoupling capacitor

Distributed decoupling capacitor

Stacked integrated circuits with redistribution lines

Post-passivation interconnect structure and methods thereof

Chip mounting structure

Electronic apparatus operable in high frequencies

Semiconductor device and method including an intertial mass element

Method to reduce resistance for a copper (CU) interconnect landing on multilayered metal contacts, and semiconductor structures formed therefrom

Stacked semiconductor devices and methods of forming same

Package structure

Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions

SELF-ALIGNED VIA PROCESS FLOW

Gate contact structure over active gate and method to fabricate same

Metal-semiconductor contact structure with doped interlayer

THIN FILM TRANSISTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR

Semiconductor structures with field effect transistor(s) having low-resistance source/drain contact(s)

High performance heat shields with reduced capacitance

Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

Multi-wafer stacking by Ox-Ox bonding

Method of fabricating a semiconductor device and semiconductor product

Self aligned via in integrated circuit

Optimized wires for resistance or electromigration

Apparatus, system, and method for wireless connection in integrated circuit packages

Wiring structure and method of forming the same, and semiconductor device including the wiring structure

Structures and methods for reliable packages

Low resistance metal contacts to interconnects

Optimized wires for resistance or electromigration

Interconnect structure having an etch stop layer over conductive lines

Low resistance metal contacts to interconnects

Formation method of semiconductor device structure

Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance

CMOS compatible thermopile with low impedance contact

Static random access memory (SRAM) device

Low profile integrated circuit (IC) package comprising a plurality of dies

Semiconductor device allowing metal layer routing formed directly under metal pad

Additional etching to increase via contact area

Manufacturing a damascene thin-film resistor

Semiconductor device having a discontinued part between a first insulating film and a second insulating film

Semiconductor device including a boundary of conductivity in a substrate

Backside device contact

Semiconductor devices

Integrated circuits having reduced dimensions between components

UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME

Method for forming interconnects

Method of manufacturing a semiconductor device

Plating method, plated component, and plating system

Bulk layer transfer wafer with multiple etch stop layers

Dual liner silicide

Array substrate, fault line repair method and display device