Detecting a void between a via and a wiring line

Passive devices for integration with three-dimensional memory devices

Semiconductor structure and process thereof

Memory device structure and fabricating method thereof

Chemoepitaxy etch trim using a self aligned hard mask for metal line to via

Sacrificial amorphous silicon hard mask for BEOL

Fin field effect transistor (finFET) device structure with interconnect structure

Fin field effect transistor (FinFET) device structure with interconnect structure

Staggered via redistribution layer (RDL) for a package and a method for forming the same

Method for manufacturing semiconductor device

CMOS-MEMS integrated device including a contact layer and methods of manufacture

Antenna apparatus and method

SWITCHING ELEMENT, AND METHOD FOR PRODUCING SWITCHING ELEMENT

Electronic device and method for fabricating the same

Oversized contacts and vias in layout defined by linearly constrained topology

Integrated circuit with elongated coupling

Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

3-D package having plurality of substrates

Calibration kits for RF passive devices

Reducing contact resistance in vias for copper interconnects

Semiconductor devices

Nonvolatile memory device and method for fabricating the same

Etch stop layer in integrated circuits

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Electronic device including moat power metallization in trench

Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same

Via formation using sidewall image transfer process to define lateral dimension

Dummy structure for chip-on-wafer-on-substrate

Method for forming semiconductor structure

Ruthenium metal feature fill for interconnects

Method of using a barrier-seed tool for forming fine pitched metal interconnects

Reducing contact resistance in vias for copper interconnects

Capacitor structure and method of manufacturing the same

Semiconductor device and manufacturing method of the same

Semiconductor device and manufacturing method of semiconductor device

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Cobalt-containing conductive layers for control gate electrodes in a memory structure

Semiconductor structure and fabrication method thereof

PROCESS FOR MANUFACTURING INTEGRATED ELECTRONIC DEVICES, IN PARTICULAR CMOS DEVICES USING A BORDERLESS CONTACT TECHNIQUE

Device, package structure and method of forming the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

Semiconductor device and manufacturing method of semiconductor device

Embedded electronic packaging and associated methods

Critical dimension shrink through selective metal growth on metal hardmask sidewalls

Critical dimension shrink through selective metal growth on metal hardmask sidewalls

Semiconductor device having a Pd-containing adhesion layer

Method of manufacturing semiconductor device

Semiconductor device having reduced drain-to-source capacitance

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

Semiconductor package assembly with facing active surfaces of first and second semiconductor die and method for forming the same

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME

Conductive paths through dielectric with a high aspect ratio for semiconductor devices

Semiconductor device

Wiring structures and semiconductor devices

Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Method and apparatus for forming multi-layered vias in sequentially fabricated circuits

System, apparatus, and method for embedding a device in a faceup workpiece

Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon

Interconnect structure and method of forming the same

Wiring board, semiconductor device, and manufacturing methods thereof

Memory cell

Semiconductor device comprising a conductive layer having an air gap

Semiconductor apparatus

Semiconductor devices and methods of manufacture thereof

Semiconductor device and method for manufacturing the same

Electromagnetic shield and associated methods

Semiconductor Device Having Gold Metallization Structures

Semiconductor device

Self aligned contact structure

Semiconductor device and method for fabricating the same

Filling cavities in an integrated circuit and resulting devices

Interconnect structure for connecting dies and methods of forming the same

Semiconductor structure and method for forming the same

Via corner engineering in trench-first dual damascene process

Semiconductor devices and methods of manufacturing the same

Air-gap scheme for BEOL process

Process of forming an electronic device including a material defining a void

Twin memory cell interconnection structure

Semiconductor device

Integrated circuit device with adaptations for multiplexed biosensing

Electronic appliance, network unit of electronic appliances, network of electronic appliances, and chip identification method

Semiconductor device

Three dimensional memory device with hybrid source electrode for wafer warpage reduction

Three dimensional memory device having well contact pillar and method of making thereof

Semiconductor device including air gaps and method for fabricating the same

ROM chip manufacturing structures

Semiconductor device and fabricating method thereof

Wire bond support structure and microelectronic package including wire bonds therefrom

FAN-OUT PACKAGE STRUCTURE INCLUDING ANTENNA

Semiconductor structure and manufacturing method thereof

Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics

Method of forming a copper based interconnect structure

2D SELF-ALIGNED VIA FIRST PROCESS FLOW

Switched-capacitor DC-to-DC converters

Semiconductor integrated circuit layout structure

Phase changing on-chip thermal heat sink

Semiconductor device and method of fabricating the same

Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch

Interconnect structure and method of forming the same

Semiconductor structures having an insulative island structure

Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device

SUBSTRATE BIAS FOR FIELD-EFFECT TRANSISTOR DEVICES

Multiheight contact via structures for a multilevel interconnect structure

Memory bit cell for reduced layout area

Semiconductor device for reducing coupling capacitance

Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices

Semiconductor device and method of manufacturing the same

Multichip integration with through silicon via (TSV) die embedded in package

Chip with a bump connected to a plurality of wirings

Reinforced wafer level package comprising a core layer for reducing stress in a solder joint and improving solder joint reliability

Memory device and method for manufacturing the same

INTEGRATED DEVICE PACKAGE COMPRISING AN ELECTROMAGNETIC (EM) PASSIVE DEVICE IN AN ENCAPSULATION LAYER, AND AN EM SHIELD

Semiconductor device having bilayer metal layer

Cut first alternative for 2D self-aligned via

Semiconductor device and manufacturing method thereof

Semiconductor devices and methods of fabricating the same

Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Semiconductor devices including a contact structure and methods of manufacturing the same

Method for forming a two-layered hard mask on top of a gate structure

Semiconductor arrangement and method of making the same

Semiconductor device and formation thereof

Thin-film transistor array substrate including gate-underlying stepped layer and etch-stopper, and organic light emitting display including the same

Multiheight contact via structures for a multilevel interconnect structure

Semiconductor device and manufacturing method of the same

Multilayer substrate, design method of multilayer substrate, manufacturing method of semiconductor device, and recording medium

Conductive traces in semiconductor devices and methods of forming same

Semiconductor device and method of manufacturing the same

Semiconductor interconnect device

Semiconductor devices and methods of manufacturing the same

Nonvolatile semiconductor memory device including pillars buried inside through holes

Reliable packaging and interconnect structures

Self-forming metal barriers

Interconnect structures and methods of forming same

Semiconductor device including cell region stacked on peripheral region and method of fabricating the same

Thin film transistor array substrate and organic light-emitting display apparatus including the same

Three-dimensional integration schemes for reducing fluorine-induced electrical shorts

Integrated circuit and semiconductor device

Semiconductor device and method of fabricating the same

Reliable microstrip routing for electronics components

Stress reduction apparatus

Integration of heat spreader for beol thermal management

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Protecting layer in a semiconductor structure

Polyhexahydrotriazine dielectrics

Methods for multi-wire routing and apparatus implementing same

Polyhexahydrotriazine dielectrics

Memory device

Semiconductor device and method for manufacturing the same

TFT array substrate, method of manufacturing the same and display device

Semiconductor memory devices

Three Dimensional Semiconductor Memory Devices and Methods of Fabricating the Same

Semiconductor memory device

Mask read-only memory array, memory device, and fabrication method thereof

Process for forming package-on-package structures

Semiconductor devices including a capping layer

Semiconductor device and a method of manufacturing the same

STRUCTURED INTEGRATED CIRCUIT DEVICE WITH MULTIPLE CONFIGURABLE VIA LAYERS

Metallic device having mobile element in a cavity of the BEOL of an integrated circuit

Three-dimensional semiconductor device

Stacked interconnect structure and method of making the same

Methods of forming wiring structures including a plurality of metal layers

Semiconductor constructions and methods of forming intersecting lines of material

Via leakage and breakdown testing

CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Efficient buried oxide layer interconnect scheme

Non-volatile memory device having vertical structure and method of operating the same

Semiconductor device with series connected inverters having different number of active regions

Nanowire or 2D material strips interconnects in an integrated circuit cell

Systems and methods for a sequential spacer scheme

Metal bond pad with cobalt interconnect layer and solder thereon

Semiconductor structures having low resistance paths throughout a wafer

Package on package architecture and method for making

Semiconductor device and method for fabricating the same

Air-gap forming techniques for interconnect structures

Methods for patterning a target layer through fosse trenches using reverse sacrificial spacer lithography

Method of forming masks

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PATTERN OVERLAY INSPECTION METHOD

Storage device with contacts contacting different wiring layers and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device and electronic device

Semiconductor device

Metallic etch stop layer in a three-dimensional memory structure

Semiconductor device and semiconductor memory device

Bumpless build-up layer package with pre-stacked microelectronic devices

Cooling channels in 3DIC stacks

Semiconductor device and method of forming PoP semiconductor device with RDL over top package

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Ultrathin multilayer metal alloy liner for nano Cu interconnects

Semiconductor device and wafer level package including such semiconductor device

Power and ground routing of integrated circuit devices with improved IR drop and chip performance

Semiconductor device structure and method for forming the same

Semiconductor device structure and method for forming the same

Multilevel interconnect structure and methods of manufacturing the same

METHODS OF FORMING WIRING STRUCTURES IN A SEMICONDUCTOR DEVICE

Device manufacture and packaging method thereof

Semiconductor device and method of manufacturing semiconductor device

Metal interconnect structure and method for fabricating the same

Semiconductor device and method of forming stacked vias within interconnect structure for FO-WLCSP

Semiconductor device and method to minimize stress on stack via

Structure for die probing

Method and apparatus for bond-pad charging protection of reference transistor test structures

Structure and formation method of damascene structure

ULTRATHIN MULTILAYER METAL ALLOY LINER FOR NANO CU INTERCONNECTS

Three-dimensional three-port bit cell and method of assembling same

Carbon conductive structure and method of manufacturing the same

Resistive memory array and fabricating method thereof

Semiconductor memory device and production method thereof

STACKED SEMICONDUCTOR STRUCTURE

Techniques for enhancing fracture resistance of interconnects

Crystalline layer stack for forming conductive layers in a three-dimensional memory structure

Method and apparatus for protecting metal interconnect from halogen based precursors

Polymer member based interconnect

Semiconductor device allowing metal layer routing formed directly under metal pad

Twisted array design for high speed vertical channel 3D NAND memory

Stacked damascene structures for microelectronic devices

Semiconductor device having non-magnetic single core inductor and method of producing the same

Hybrid interconnect scheme and methods for forming the same

Semiconductor device

Interconnect structure and method of forming the same

Ultrathin multilayer metal alloy liner for nano Cu interconnects

Semiconductor memory device

Testing of semiconductor devices and devices, and designs thereof

Electromechanical nonvolatile memory

Semiconductor apparatus

Semiconductor devices including conductive features with capping layers and methods of forming the same

Self-aligned via and air gap

Semiconductor device for preventing crack in pad region and fabricating method thereof

Composite contact plug structure and method of making same

Vehicle security network device and design method therefor

Low temperature fabrication of lateral thin film varistor

Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions

Memory metal scheme

System-on-chip devices and methods of designing a layout therefor

Semiconductor device security

Dummy metal structure and method of forming dummy metal structure

Methods of making integrated circuit assembly with faraday cage and including a conductive ring

Semiconductor device security

Inductor for semiconductor integrated circuit

Integrated circuit barrierless microfluidic channel

Integrated circuits and methods for fabricating integrated circuits with self-aligned vias

Semiconductor device and semiconductor device fabrication method

Through substrate via scan cell with comparator mux, and flip-flop

Thin film transistor substrate

Vertical type memory device

Semiconductor device

Semiconductor device

Apparatus and method for generating identification key

Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof

Semiconductor device with air gap and method for fabricating the same

Semiconductor devices having staggered air gaps

Microelectronic assemblies formed using metal silicide, and methods of fabrication

Capacitor in post-passivation structures and methods of forming the same

Systems and methods to enhance passivation integrity

Interconnect structure having large self-aligned vias

Semiconductor Devices And Fabrication Methods With Improved Word Line Resistance and Reduced Salicide Bridge Formation

Conformal low temperature hermetic dielectric diffusion barriers

Semiconductor device including air gaps and method of fabricating the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE

Three-dimensional (3D) semiconductor devices and methods of fabricating 3D semiconductor devices

Metal layers for a three-port bit cell

Package structures and methods of forming the same

Middle-of-line integration methods and semiconductor devices

Layer structure including diffusion barrier layer and method of manufacturing the same

Semiconductor arrangement and formation thereof

Self-aligned integrated line and via structure for a three-dimensional semiconductor device

Semiconductor devices including sealing regions and decoupling capacitor regions

Semiconductor device, layout design and method for manufacturing a semiconductor device

Embedded packaging for devices and systems comprising lateral GaN power transistors

Magnetic sidewalls for write lines in field-induced MRAM and methods of manufacturing them

Enhanced channel mobility three-dimensional memory structure and method of making thereof

Tungsten for wordline applications

Etchstop layers and capacitors

Device and method for generating identification key

Angled ion beam processing of heterogeneous structure

Microelectronic devices with through-silicon vias and associated methods of manufacturing

INTEGRATED CIRCUIT DEVICE INCLUDING MULTIPLE VIA CONNECTORS AND A METAL STRUCTURE HAVING A LADDER SHAPE

Mechanisms for forming metal-insulator-metal (MIM) capacitor structure

SLOT DESIGNS IN WIDE METAL LINES

Integrated device package comprising a magnetic core inductor with protective ring embedded in a package substrate

SELECTIVE CONDUCTIVE BARRIER LAYER FORMATION

Storage element, storage device, and signal processing circuit

Memory circuit, layout of memory circuit, and method of forming layout

Semiconductor devices having an electro-static discharge protection structure

Folded ballistic conductor interconnect line

Semiconductor devices and methods for forming the same

Electro-migration enhancing method for self-forming barrier process in copper mettalization

Semiconductor device having wires

Semiconductor device and fabricating process for the same

Non-volatile memory device having vertical structure and method of operating the same

Image sensor packages and methods of fabricating the same

Semiconductor memory device

Semiconductor device having contact pads

3D package with through substrate vias

Damascene re-distribution layer (RDL) in fan out split die application

Semiconductor device having a cylindrical shaped conductive portion

Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same

Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device