THIN FILM RESISTOR INTEGRATION IN COPPER DAMASCENE METALLIZATION

Composite contact via structure containing an upper portion which fills a cavity within a lower portion

Semiconductor device and structure

Device comprising a ductile layer and method of making the same

Patterning approach for improved via landing profile

Method of fabricating a semiconductor device with reduced leak paths

Interconnect structure and manufacturing method thereof

Electrical connection structure with via hole, array substrate and display device

Hybrid bonding with uniform pattern density

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Integrated circuit devices and methods

Integrated circuit having slot via and method of forming the same

Fishbone structure enhancing spacing with adjacent conductive line in power network

Semiconductor device and method of manufacturing the same

Lateral charge storage region formation for semiconductor wordline

Method for preventing copper contamination in metal-insulator-metal (MIM) capacitors

Dicing method for power transistors

Semiconductor device with reduced via resistance

Electronic package and method of connecting a first die to a second die to form an electronic package

Tank circuit structure and method of making the same

CHIP PACKAGE AND FABRICATION METHOD THEREOF

Semiconductor device structures with improved planarization uniformity, and related methods

Semiconductor memory device and method for manufacturing same

Semiconductor device

Hybrid bonding with air-gap structure

THREE-DIMENSIONAL INTEGRATED STRUCTURE COMPRISING AN ANTENNA CROSS REFERENCE TO RELATED APPLICATIONS

Support structure for barrier layer of semiconductor device

Stacked via structure for metal fuse applications

SELF-ALIGNED VIA INTERCONNECT STRUCTURES

Localized high density substrate routing

Stacked multilayer structure and manufacturing method thereof

Self-aligned via interconnect structures

Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects

Semiconductor device with reduced via resistance

Interconnect structures incorporating air-gap spacers

LTPS TFT substrate structure and method of forming the same

Semiconductor device and method of manufacturing same

Contact structure and formation thereof

Interconnect structure with misaligned metal lines coupled using different interconnect layer

Chip package having a laser stop structure

Interconnection structure and manufacturing method thereof

Semiconductor device and method of manufacturing the same

Forming layers of materials over small regions by selective chemical reaction including limiting enchroachment of the layers over adjacent regions

Package apparatus and manufacturing method thereof

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Physical unclonable interconnect function array

Semiconductor devices having low contact resistance and low current leakage

Deformable electronic device and methods of providing and using deformable electronic device

Three-dimensional integrated circuit integration

Subtractive etch interconnects

Semiconductor devices having expanded recess for bit line contact

RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES

Through substrate vias with improved connections

Self-aligned interconnection for integrated circuits

Semiconductor device with multi-layer metallization

Titanium tungsten liner used with copper interconnects

Semiconductor structure and fabrication method thereof

Method of fabricating semiconductor device

Integrated circuits with capacitors and methods of producing the same

Backside through vias in a bonded structure

Picture frame stiffeners for microelectronic packages

Compact semiconductor package and related methods

Conductive structure and manufacturing method thereof, and electronic device and manufacturing method thereof

Integrated device package comprising photo sensitive fill between a substrate and a die

Semiconductor device and manufacturing method of the same

Designed-based interconnect structure in semiconductor structure

Semiconductor device and method for manufacturing the same

HIGH ASPECT RATIO STRUCTURE

SYSTEM, APPARATUS, AND METHOD FOR SEMICONDUCTOR PACKAGE GROUNDS

Array substrate, display panel and display apparatus

Three-dimensional semiconductor memory devices

Air trench in packages incorporating hybrid bonding

Monolithic stacked integrated circuits with a redundant layer for repairing defects

Optimized wires for resistance or electromigration

SEMICONDUCTOR STRUCTURE WITH BOTTOM-FREE LINER FOR TOP CONTACT

Semiconductor device and fabrication method thereof

Interconnect structures with fully aligned vias

Substrate-less stackable package with wire-bond interconnect

Semiconductor structure and fabrication method thereof

POWER REDUCED COMPUTING

Semiconductor structure and fabrication method thereof

Self-aligned via interconnect structures

Methods of fabricating a semiconductor device having a via structure and an interconnection structure

Method of forming semiconductor packages having through package vias

Self-aligned contacts

SEMICONDUCTOR PACKAGE

Different scaling ratio in FEOL/ MOL/ BEOL

Opening fill process and structure formed thereby

Package structure and manufacturing method thereof

Interconnect structure for an integrated circuit and method of fabricating an interconnect structure

MIMCAP STRUCTURE IN A SEMICONDUCTOR DEVICE PACKAGE

Metal-insulator-metal on-die capacitor with partial vias

Semiconductor devices having a TSV, a front-side bumping pad, and a back-side bumping pad

Contact module for optimizing emitter and contact resistance

ELECTRONIC PACKAGE

TFT substrates and the manufacturing method thereof

Methods of forming stacked microelectronic dice embedded in a microelectronic substrate

Method for forming interconnect structure that avoids via recess

Method and structure to contact tight pitch conductive layers with guided vias

PRECISION INTRALEVEL METAL CAPACITOR FABRICATION

Voltage contrast characterization structures and methods for within chip process variation characterization

Vias and methods of formation thereof

Set of stepped surfaces formation for a multilevel interconnect structure

Metal segments as landing pads and local interconnects in an IC device

Integrated thinfilm resistor and MIM capacitor with a low serial resistance

Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods

Radio-frequency integrated circuits including inductors and methods of fabricating the same

Semiconductor device and method for fabricating the same

METHOD AND APPARATUS FOR A HIGH YIELD CONTACT INTEGRATION SCHEME

Self-aligned via process flow

High speed electroplating metallic conductors

Low-noise arrangement for very-large-scale integration differential input/output structures

Semiconductor devices and methods of manufacture thereof having guard ring structure

Wiring Structures and Methods of Forming the Same

Semiconductor device with damascene bit line and method for fabricating the same

Methods for thermally forming a selective cobalt layer

Semiconductor package including dielectric layers defining via holes extending to component pads

Dual sided circuit for surface mounting

Phase changing on-chip thermal heat sink

APPARATUS AND METHOD FOR GENERATING DIGITAL VALUE

Segmented power transistor

Semiconductor devices including contact patterns having a rising portion and a recessed portion

Electrostatic discharge protection structure and method

Method of fabricating a tungsten plug in a semiconductor device

Methods of forming an improved via to contact interface by selective formation of a conductive capping layer

Bond pad structure with dual passivation layers

Method for manufacturing copper layer

Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects

Electrically conductive interconnect including via having increased contact surface area

Integrated circuitry

Via structure for optimizing signal porosity

Buried etch stop layer for damascene bit line formation

Memory cell having multi-level word line

Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer

Air gaps structures for damascene metal patterning

Semiconductor device, display driver integrated circuit including the device, and display device including the device

Metal-insulator-metal back end of line capacitor structures

Planar passivation for pads

Strain detection structures for bonded wafers and chips

Semiconductor device and method

Oversized contacts and vias in layout defined by linearly constrained topology

Fuse structure and method of blowing the same

Precut metal lines

Low-Resistance Interconnects and Methods of Making Same

Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

Semiconductor structures and fabrication methods thereof

EMBEDDED PACKAGES, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME

Semiconductor device structure with conductive pillar and conductive line and method for forming the same

Two step metallization formation

Systems and method for ohmic contacts in silicon carbide devices

Batch contacts for multiple electrically conductive layers

Vertical breakdown protection layer

Low energy etch process for nitrogen-containing dielectric layer

Semiconductor device with metal think film and via

Chip package structure

Dummy metal structure and method of forming dummy metal structure

Fabrication method of interconnect structure

Etch stop layer in integrated circuits

Vertical type memory device

Self aligned active trench contact

Metallisation for semiconductor device

Interconnects through dielecric vias

Integrated circuit with elongated coupling

FIN-SHAPED FIELD-EFFECT TRANSISTOR WITH A GERMANIUM EPITAXIAL CAP AND A METHOD FOR FABRICATING THE SAME

LOW CAPACITANCE BALLISTIC CONDUCTOR SIGNAL LINES

INTERLAYER BALLISTIC CONDUCTOR SIGNAL LINES

Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects

Semiconductor device and method of manufacturing the same

Embedded package and method thereof

Semiconductor package assembly

Discrete flexible interconnects for modules of integrated circuits

Semiconductor device and manufacturing method thereof

Semiconductor device structure and method for forming the same

System on chip

Semiconductor package and method of manufacturing the same

Memory device and manufacturing method thereof

Stacked conductor structure and methods for manufacture of same

Semiconductor structure including a through electrode, and method for forming the same

Dimension-controlled via formation processing

Display having vertical gate line extensions and minimized borders

Display having vertical gate line extensions and touch sensor

Non-volatile random access memory (NVRAM)

MRAM integration with low-K inter-metal dielectric for reduced parasitic capacitance

Microelectromechanical system (MEMS) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3D IC) integration

Fan out package structure and methods of forming

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor device and process

SYSTEM, APPARATUS, AND METHOD OF INTERCONNECTION IN A SUBSTRATE

Air gap structure and method

Device resulting from printing minimum width semiconductor features at non-minimum pitch

Integration of heat spreader for beol thermal management

Semiconductor device structure and manufacturing methods

FAN-OUT WAFER LEVEL PACKAGE CONTAINING BACK-TO-BACK EMBEDDED MICROELECTRONIC COMPONENTS AND ASSEMBLY METHOD THEREFOR

CARBON NANOTUBE INTERCONNECT STRUCTURE, AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method for forming the same

Fine line space resolution lithography structure for integrated circuit features using double patterning technology

PACKAGE SUBSTRATE

Mitigating electromigration effects using parallel pillars

Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding thereto

Semiconductor device having improved heat-dissipation characteristics

Sample stack structure and method for preparing the same

Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Non-volatile semiconductor memory device and manufacturing method thereof

Semiconductor substrate and semiconductor package structure

Nonvolatile semiconductor memory device and method of manufacturing the same

Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods

Polymer member based interconnect

Semiconductor memory device with electrode connecting to circuit chip through memory array chip

Semiconductor package

Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device

Additional etching to increase via contact area

Semiconductor package structure including die and substrate electrically connected through conductive segments

Substrate structure and method of manufacturing the same

Semiconductor package

Semiconductor device and a method of manufacturing the same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Single damascene interconnect structure

SEMICONDUCTOR DEVICE ETCHING FOR RC DELAY IMPROVEMENT

Semiconductor package having conductive pillars

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Copper contact plugs with barrier layers

Hydrogen-free silicon-based deposited dielectric films for nano device fabrication

Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime

Semiconductor device having mesh-patterned wirings

SEMICONDUCTOR DEVICE

Metal cap apparatus and method

Method and structure to reduce the electric field in semiconductor wiring interconnects

Semiconductor device and structure therefor

Semiconductor device and method of manufacturing the same

Designed-based interconnect structure in semiconductor structure

Method and structure to reduce the electric field in semiconductor wiring interconnects

Multiheight contact via structures for a multilevel interconnect structure

Method for forming three-dimensional interconnection, circuit arrangement comprising three-dimensional interconnection, and metal film-forming composition for three-dimensional interconnection

Semiconductor device having stable structure and method of manufacturing the same

Electric connection element manufacturing method

Structure of dual damascene structures having via hole and trench

Method of making openings in a semiconductor device with reduced residue by transferring layers

Hydrogen-free silicon-based deposited dielectric films for nano device fabrication

Method and system for via retargeting

Liquid crystal display

POWER TRANSISTOR WITH DISTRIBUTED DIODES

Power transistor with distributed gate

Hybrid carbon-metal interconnect structures

Integrated thermoelectric generator

Semiconductor device and fabrication method therefor

Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same

Semiconductor device, manufacturing method thereof, and electronic device

Semiconductor devices and methods of forming the same

Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof

Semiconductor structure including a through electrode, and method for forming the same

CHIP PACKAGE MODULE AND PACKAGE SUBSTRATE

Wafer with liquid molding compound and post-passivation interconnect

Fabricating pillar solder bump

Hydrogen-free silicon-based deposited dielectric films for nano device fabrication

E-fuse structure of semiconductor device

Wiring for semiconductor device and method of forming same

Semiconductor device and manufacturing method therefor

Self-aligned back end of line cut

Semiconductor device, method of manufacturing the same, and electronic device

PACKAGE SUBSTRATES INCLUDING EMBEDDED CAPACITORS

Array substrate structure and contact structure

Semiconductor device

Apparatus for high speed ROM cells

SEMICONDUCTOR DEVICE

3DIC package and methods of forming the same

Buffer layer(s) on a stacked structure having a via

Via pre-fill on back-end-of-the-line interconnect layer

Semiconductor device

Interconnect structure

Interconnect structures with fully aligned vias

Semiconductor device and method

Interconnect structure and method of forming the same

Phase changing on-chip thermal heat sink

Structure and formation method of damascene structure

Long-term heat treated integrated circuit arrangements and methods for producing the same

Method for improving adhesion between porous low k dielectric and barrier layer

Hydrogen-free silicon-based deposited dielectric films for nano device fabrication

Via density in radio frequency shielding applications

Semiconductor device having control conductors

Thin film transistor, manufacturing method thereof, array substrate and display apparatus

FINFET SEMICONDUCTOR DEVICES WITH STRESSED LAYERS

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Electrode lead-out structure, array substrate and display device

Semiconductor structure and manufacturing method of the same

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Interconnect structures for integrated circuits and their formation

Meander line resistor structure

Power semiconductor package having vertically stacked driver IC

Semiconductor device packages, packaging methods, and packaged semiconductor devices

ROUTING PATHS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

Semiconductor devices with close-packed via structures having in-plane routing and method of making same

Methods for fabricating integrated circuits having device contacts

Copper wire and dielectric with air gaps

Method for forming seed layer on high-aspect ratio via and semiconductor device having high-aspect ratio via formed thereby

Array substrate and manufacturing method thereof, display device

Array substrate, method for fabricating the same and display device

Memory device structure

Semiconductor device with reduced via resistance

E-fuse structure with methods of fusing the same and monitoring material leakage